riscv/rocket-chip
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Author SHA1 Message Date
Howard Mao
485d8d7f9c fix nasti converter tests 2016-04-12 15:38:55 -07:00
Howard Mao
b2e15cd9bc NASTI to SMI converter test should also test TL to NASTI conversion 2016-04-12 15:38:55 -07:00
Howard Mao
0c562277db test Nasti to SMI converter with SMI datawidth being different 2016-04-12 15:38:55 -07:00
Howard Mao
152645b1bc use manager_id instead of client_id in GrantFromSrc and FinishToDst 2016-04-07 11:20:16 -07:00
Howard Mao
f88b6932ce don't add pending reads if data is already available 2016-04-06 15:43:21 -07:00
Christopher Celio
2d6f35525e Added Field[Int] to SFMALatency/DFMALatency params 2016-04-06 14:50:57 -07:00
mwachs5
a81334f505 Update README links to point to this repo 2016-04-06 14:10:04 -07:00
Matthew Naylor
b2eabf4a9f Add tracegen scripts inc. bugfix from @mwachs5 
A step towards moving the tracegen scripts from rocket-chip to
groundtest.  I will raise an issue requesting that the scripts are now
removed from rocket-chip by someone with write access.

I have updated the README to account for the move.

This commit includes a bugfix from @mwachs5 (with slight mods by me)
relating to potential division by zero in toaxe.py.
 2016-04-06 15:15:48 +01:00
Howard Mao
31e145eaf0 fix BroadcastHub allocation and routing 2016-04-05 16:21:18 -07:00
Howard Mao
f68a7dabdf fix AXI -> TL converter 2016-04-04 19:42:25 -07:00
Howard Mao
f956d4edfb NASTI does not right-justify data; fix in converter 2016-04-01 20:55:00 -07:00
Henry Cook
c292a07ace Bugfix for merged voluntary releases in L2Cache. 
Track pending release beats for voluntary releases that are merged by Acquire Trackers.
Closes #23 and #24.
 2016-04-01 19:57:47 -07:00
Andrew Waterman
7285f5e6bf Don't drive D$ kill/phys signals for SimpleHellaCacheIF 
They don't do anything.
 2016-04-01 19:31:54 -07:00
Andrew Waterman
51e0870e23 Separate I$ and D$ interface signals that span clock cycles 
For example, Decopuled[HellaCacheReq].bits.kill doesn't make sense,
since it doesn't come the same cycle as ready/valid.
 2016-04-01 19:30:39 -07:00
Howard Mao
d66d8f0cd4 fix SMI converter 2016-04-01 18:32:15 -07:00
Andrew Waterman
c4c6bd1040 Bump rocket. 
Closes #84.
 2016-04-01 18:20:32 -07:00
Andrew Waterman
b43a85e2e8 Make ExampleSmallConfig/DefaultRV32Config smaller 2016-04-01 18:18:08 -07:00
Andrew Waterman
6878e3265f Default RowBits to TileLink width, not XLen 2016-04-01 18:18:08 -07:00
Andrew Waterman
46d7dceb1e Disable printf/assert during reset 2016-04-01 18:18:08 -07:00
Andrew Waterman
cd9e07d8e7 Update sbt to 0.13.11 2016-04-01 18:18:08 -07:00
Andrew Waterman
bd3dba7f66 Fix LR/SC livelock bug 
Closes #74.
 2016-04-01 18:18:08 -07:00
Henry Cook
35d02c5096 LRSC fix. RocketChipNetwork moved to uncore. 2016-04-01 18:09:00 -07:00
Andrew Waterman
dc662f28a0 Specify width on s1_pc to avoid width inference problem 2016-04-01 17:28:42 -07:00
Andrew Waterman
72f7f71eb5 No need to allow finishes to be sent in s_refill_resp state 
This is a hold-over from when writebacks needed finish messages.
 2016-04-01 16:19:57 -07:00
Henry Cook
82bdf3afcb Fix LRSC starvation bug by punching Finish messages out to caching clients via a new TileLinkNetworkPort. 2016-04-01 16:17:27 -07:00
Henry Cook
78bc18736e LRSC startvation fix: HellaCache generates its own Finish messages again. 2016-04-01 16:04:25 -07:00
Andrew Waterman
37b9051762 No need to validate npc if BTB is disabled 2016-04-01 15:54:57 -07:00
Andrew Waterman
4480d1e817 Don't compile BTB when nEntries=0 2016-04-01 15:14:45 -07:00
Andrew Waterman
d406dc1231 Remove vestigial BTB enable option 2016-04-01 15:14:34 -07:00
Andrew Waterman
8957b5e973 Improve simulation speed of BasicCrossbar 2016-04-01 13:28:11 -07:00
Howard Mao
5337c7d22d add more complicated memtests to travis 2016-03-31 18:42:14 -07:00
Howard Mao
4f06a5ff6b add memtest config for testing memory channel mux 2016-03-31 18:41:56 -07:00
Howard Mao
5a74a9b1e7 switch memory interconnect from AXI to TileLink 2016-03-31 18:18:30 -07:00
Howard Mao
3083bbca21 fix TileLink arbiters and add memory interconnect and memory selector 2016-03-31 18:15:51 -07:00
Henry Cook
54dd82ff76 bugfix for WB data buffer 2016-03-31 17:53:49 -07:00
Christopher Celio
1792d01ce1 fix leaky assert in nbdcache 
Squash of #33.
 2016-03-31 15:56:14 -07:00
Howard Mao
6d5c98da7d point submodule pointer to proper commit hash 2016-03-31 15:03:33 -07:00
Howard Mao
7c3b57b8fa switch MMIO network to TileLink 2016-03-31 14:30:10 -07:00
Matthew Naylor
6d3bba6cff Tweaks to README.md 
Remove occurrences of ../scripts/ and instead state that it must be in
your PATH.  Also drop the content introducing the isit script as
tracegen+check.sh subsumes this.
 2016-03-31 14:22:09 -07:00
mwachs5
22e7b3ff2f Update README.md 
- adding instructions of how to run with groundtest
- correct some MD syntax in README
- add some spaces
- minor changes to wording
- remove spurious 'class'
- add commands for running w/ TraceGenConfig
- add code from http://www.cl.cam.ac.uk/~mn416/tracegen.html
- Update README.md
- add WSO note
- correct some syntax within the code blocks and add note about run-asm-tests, run-bmark-tests
- Add one more command to the "quick reference" to show the complete flow
- Correct WSO to WMO
- Add information about tracegen+check.sh
- Use tracegen.py commands instead of running the emulator directly
- added a missing newline
- remove extra head command
 2016-03-31 14:20:14 -07:00
Howard Mao
cf363b1fe4 add TileLink interconnect generator 2016-03-31 14:12:55 -07:00
Andrew Waterman
adb7eacf6e Fix Chisel3 build for XLen=32 2016-03-30 22:48:51 -07:00
Andrew Waterman
70664bbca0 Fix Chisel3 build for UseVM=false 2016-03-30 22:48:31 -07:00
Howard Mao
ab540d536a bump uncore for split metadata chisel3 fix 2016-03-30 22:11:45 -07:00
Howard Mao
d78066db5c chisel3 fix for split metadata 2016-03-30 22:11:19 -07:00
Howard Mao
c831a0a4e5 use scala firrtl instead of stanza firrtl 2016-03-30 19:35:25 -07:00
Howard Mao
be612e3843 bump rocket and uncore 2016-03-30 19:23:19 -07:00
Howard Mao
3d990bdbef workaround for Chisel3 name-aliasing issue 2016-03-30 19:15:22 -07:00
Howard Mao
c081a36893 Revert "Bump chisel3 and firrtl, add support for firrtl $ delimiter" 
This reverts commit 5378f79b50.
 2016-03-30 19:06:32 -07:00
Howard Mao
e77900f540 Revert "switch back to Chisel2 for verilog build for now" 
This reverts commit 3673365b08.
 2016-03-30 19:00:38 -07:00