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Commit Graph

38 Commits

Author SHA1 Message Date
Andrew Waterman
31060ea8ae Fix fubar long-latency writeback control logic
Load miss writebacks happening at the same time as multiplication
wasn't working.  Hopefully this does it.
2014-01-14 04:02:43 -08:00
Andrew Waterman
f12bbc1e43 working RoCC AccumulatorExample 2013-09-14 22:34:53 -07:00
Henry Cook
3a266cbbfa final Reg changes 2013-08-15 15:28:15 -07:00
Henry Cook
1a9e43aa11 initial attempt at upgrade 2013-08-12 10:39:11 -07:00
Henry Cook
9abdf4e154 Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object. 2013-07-23 20:27:58 -07:00
Henry Cook
273bd34091 Generalized mem arbiter, moved to uncore. Support for multiple banks when acking grants. 2013-03-20 15:53:36 -07:00
Andrew Waterman
ea9d0b771e remove aborts; simplify probes 2013-03-19 15:29:40 -07:00
Henry Cook
e0361840bd writebacks on release network pass asm tests and bmarks 2013-02-28 18:11:40 -08:00
Henry Cook
6b00e7ff74 New TileLink bundle names 2013-01-21 17:18:23 -08:00
Henry Cook
a2fa3fd04d Refactored packet headers/payloads 2013-01-15 15:50:37 -08:00
Henry Cook
e1225c5114 standardize IO naming convention 2013-01-07 13:41:36 -08:00
Andrew Waterman
8dce89703a new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
2012-11-16 02:39:33 -08:00
Andrew Waterman
4d1ca8ba3a remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
2012-11-06 08:13:44 -08:00
Andrew Waterman
c5b93798fb factor out more global constants 2012-11-05 23:52:32 -08:00
Henry Cook
5d2a470215 all rocket-specific arbiters in one file and refactored traits slightly 2012-10-15 16:05:32 -07:00
Henry Cook
dfdfddebe8 constants as traits 2012-10-07 22:20:03 -07:00
Huy Vo
e909093f37 factoring out uncore into separate uncore repo 2012-10-01 16:08:41 -07:00
Andrew Waterman
f42c6afed2 decouple all interfaces between tile and top
also, add an "incoherent" bit to tilelink to indicate no probes needed
2012-07-17 22:55:40 -07:00
Huy Vo
a99cebb483 ioDecoupled -> FIFOIO, ioPipe -> PipeIO 2012-06-06 18:22:56 -07:00
Huy Vo
04304fe788 moving util out into Chisel standard library 2012-06-06 12:51:26 -07:00
Huy Vo
7408c9ab69 removing wires 2012-05-24 10:42:39 -07:00
Henry Cook
ed79ec98f7 Refactored coherence better from uncore hub, better coherence function names 2012-04-09 23:29:31 -07:00
Andrew Waterman
5f12990dfb support memory transaction aborts 2012-03-06 00:35:02 -08:00
Henry Cook
9d7707a0a2 Made xact_rep an ioValid, removed has_data member 2012-03-01 18:24:21 -08:00
Andrew Waterman
012da6002e replace tile memory interface with ioTileLink
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
2012-02-29 03:10:47 -08:00
Andrew Waterman
c99f6bbeb7 separate memory request command and data
also, merge some VLSI/C++ test harness functionality
2012-02-28 19:06:23 -08:00
Andrew Waterman
2b1c07c723 replace ioDCache with ioMem 2012-02-27 18:36:09 -08:00
Yunsup Lee
94ba32bbd3 change package name and sbt project name to rocket 2012-02-25 17:09:26 -08:00
Andrew Waterman
6135615104 unify cache backend interfaces; generify arbiter 2012-02-20 00:51:48 -08:00
Andrew Waterman
7034c9be65 new htif protocol and implementation
You must update your fesvr and isasim!
2012-02-19 23:15:45 -08:00
Yunsup Lee
6bdf9dc513 hwacha integration: now it compiles correctly! 2012-02-14 23:34:57 -08:00
Christopher Celio
1be9d15944 Fixed bug regarding case sensitivity regarding ioICache,ioDCache 2012-02-07 14:07:42 -08:00
Henry Cook
1d76255dc1 new chisel version jar and find and replace INPUT and OUTPUT 2012-01-18 14:39:57 -08:00
Andrew Waterman
938b142d64 require writes to memory to be uninterrupted 2012-01-03 18:41:53 -08:00
Andrew Waterman
56c4f44c2a hellacache returns!
but AMOs are unimplemented.
2011-12-12 06:49:39 -08:00
Andrew Waterman
218f63e66e code cleanup/parameterization 2011-12-09 00:42:43 -08:00
Rimas Avizienis
9aca403aa8 more itlb integration & cleanup 2011-11-09 23:18:14 -08:00
Rimas Avizienis
c06e2d16e4 initial commit of rocket chisel project, riscv assembly tests and benchmarks 2011-10-25 23:02:47 -07:00