Andrew Waterman
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31060ea8ae
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Fix fubar long-latency writeback control logic
Load miss writebacks happening at the same time as multiplication
wasn't working. Hopefully this does it.
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2014-01-14 04:02:43 -08:00 |
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Andrew Waterman
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f12bbc1e43
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working RoCC AccumulatorExample
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2013-09-14 22:34:53 -07:00 |
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Henry Cook
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3a266cbbfa
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final Reg changes
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2013-08-15 15:28:15 -07:00 |
|
Henry Cook
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1a9e43aa11
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initial attempt at upgrade
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2013-08-12 10:39:11 -07:00 |
|
Henry Cook
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9abdf4e154
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Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
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2013-07-23 20:27:58 -07:00 |
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Henry Cook
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273bd34091
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Generalized mem arbiter, moved to uncore. Support for multiple banks when acking grants.
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2013-03-20 15:53:36 -07:00 |
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Andrew Waterman
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ea9d0b771e
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remove aborts; simplify probes
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2013-03-19 15:29:40 -07:00 |
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Henry Cook
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e0361840bd
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writebacks on release network pass asm tests and bmarks
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2013-02-28 18:11:40 -08:00 |
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Henry Cook
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6b00e7ff74
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New TileLink bundle names
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2013-01-21 17:18:23 -08:00 |
|
Henry Cook
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a2fa3fd04d
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Refactored packet headers/payloads
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2013-01-15 15:50:37 -08:00 |
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Henry Cook
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e1225c5114
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standardize IO naming convention
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2013-01-07 13:41:36 -08:00 |
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Andrew Waterman
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8dce89703a
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new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
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2012-11-16 02:39:33 -08:00 |
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Andrew Waterman
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4d1ca8ba3a
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remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
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2012-11-06 08:13:44 -08:00 |
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Andrew Waterman
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c5b93798fb
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factor out more global constants
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2012-11-05 23:52:32 -08:00 |
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Henry Cook
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5d2a470215
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all rocket-specific arbiters in one file and refactored traits slightly
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2012-10-15 16:05:32 -07:00 |
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Henry Cook
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dfdfddebe8
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constants as traits
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2012-10-07 22:20:03 -07:00 |
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Huy Vo
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e909093f37
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factoring out uncore into separate uncore repo
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2012-10-01 16:08:41 -07:00 |
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Andrew Waterman
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f42c6afed2
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decouple all interfaces between tile and top
also, add an "incoherent" bit to tilelink to indicate no probes needed
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2012-07-17 22:55:40 -07:00 |
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Huy Vo
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a99cebb483
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ioDecoupled -> FIFOIO, ioPipe -> PipeIO
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2012-06-06 18:22:56 -07:00 |
|
Huy Vo
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04304fe788
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moving util out into Chisel standard library
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2012-06-06 12:51:26 -07:00 |
|
Huy Vo
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7408c9ab69
|
removing wires
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2012-05-24 10:42:39 -07:00 |
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Henry Cook
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ed79ec98f7
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Refactored coherence better from uncore hub, better coherence function names
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2012-04-09 23:29:31 -07:00 |
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Andrew Waterman
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5f12990dfb
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support memory transaction aborts
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2012-03-06 00:35:02 -08:00 |
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Henry Cook
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9d7707a0a2
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Made xact_rep an ioValid, removed has_data member
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2012-03-01 18:24:21 -08:00 |
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Andrew Waterman
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012da6002e
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replace tile memory interface with ioTileLink
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
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2012-02-29 03:10:47 -08:00 |
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Andrew Waterman
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c99f6bbeb7
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separate memory request command and data
also, merge some VLSI/C++ test harness functionality
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2012-02-28 19:06:23 -08:00 |
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Andrew Waterman
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2b1c07c723
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replace ioDCache with ioMem
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2012-02-27 18:36:09 -08:00 |
|
Yunsup Lee
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94ba32bbd3
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change package name and sbt project name to rocket
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2012-02-25 17:09:26 -08:00 |
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Andrew Waterman
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6135615104
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unify cache backend interfaces; generify arbiter
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2012-02-20 00:51:48 -08:00 |
|
Andrew Waterman
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7034c9be65
|
new htif protocol and implementation
You must update your fesvr and isasim!
|
2012-02-19 23:15:45 -08:00 |
|
Yunsup Lee
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6bdf9dc513
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hwacha integration: now it compiles correctly!
|
2012-02-14 23:34:57 -08:00 |
|
Christopher Celio
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1be9d15944
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Fixed bug regarding case sensitivity regarding ioICache,ioDCache
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2012-02-07 14:07:42 -08:00 |
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Henry Cook
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1d76255dc1
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new chisel version jar and find and replace INPUT and OUTPUT
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2012-01-18 14:39:57 -08:00 |
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Andrew Waterman
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938b142d64
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require writes to memory to be uninterrupted
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2012-01-03 18:41:53 -08:00 |
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Andrew Waterman
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56c4f44c2a
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hellacache returns!
but AMOs are unimplemented.
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2011-12-12 06:49:39 -08:00 |
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Andrew Waterman
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218f63e66e
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code cleanup/parameterization
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2011-12-09 00:42:43 -08:00 |
|
Rimas Avizienis
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9aca403aa8
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more itlb integration & cleanup
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2011-11-09 23:18:14 -08:00 |
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Rimas Avizienis
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c06e2d16e4
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initial commit of rocket chisel project, riscv assembly tests and benchmarks
|
2011-10-25 23:02:47 -07:00 |
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