75 lines
2.2 KiB
Scala
75 lines
2.2 KiB
Scala
package Top {
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import Chisel._;
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import Node._;
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import Constants._;
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class ioMem() extends Bundle
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{
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val req_val = Bool('output);
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val req_rdy = Bool('input);
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val req_rw = Bool('output);
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val req_addr = UFix(32, 'output);
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val req_wdata = Bits(128, 'output);
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val req_tag = Bits(4, 'output);
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val resp_val = Bool('input);
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val resp_tag = Bits(4, 'input);
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val resp_data = Bits(128, 'input);
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}
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class ioArbiter extends Bundle() {
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val mem = new ioMem();
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val dcache = new ioDcache();
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// val icache = new ioIcache();
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val icache = new ioIPrefetcherMem().flip();
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}
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class rocketMemArbiter extends Component {
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val io = new ioArbiter();
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// *****************************
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// Interface to memory
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// *****************************
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// Memory request is valid if either icache or dcache have a valid request
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io.mem.req_val := (io.icache.req_val || io.dcache.req_val);
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// Set read/write bit. Icache always reads
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io.mem.req_rw := Mux(io.icache.req_val,Bool(false),io.dcache.req_rw);
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// Give priority to Icache
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io.mem.req_addr := Mux(io.icache.req_val,io.icache.req_addr,io.dcache.req_addr);
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// high bit of tag=0 for I$, tag=0 for D$
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// io.mem.req_tag := Mux(io.icache.req_val,Bits(0,4),Bits(1,4));
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io.mem.req_tag := Mux(io.icache.req_val,
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Cat(Bits(0,1), io.icache.req_tag),
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Cat(Bits(1,1), io.dcache.req_tag));
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// Just pass through write data (only D$ will write)
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io.mem.req_wdata := io.dcache.req_wdata;
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// *****************************
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// Interface to caches
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// *****************************
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// Read for request from cache if the memory is ready. Give priority to I$
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io.icache.req_rdy := io.mem.req_rdy;
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io.dcache.req_rdy := io.mem.req_rdy && !io.icache.req_val;
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// Response will only be valid for D$ or I$ not both because of tag bits
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io.icache.resp_val := io.mem.resp_val && !io.mem.resp_tag(3).toBool;
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io.dcache.resp_val := io.mem.resp_val && io.mem.resp_tag(3).toBool;
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// Feed through data to both
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io.icache.resp_data := io.mem.resp_data;
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io.dcache.resp_data := io.mem.resp_data;
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io.icache.resp_tag := io.mem.resp_tag(2,0);
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io.dcache.resp_tag := io.mem.resp_tag(2,0);
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}
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}
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