79 lines
2.5 KiB
Scala
79 lines
2.5 KiB
Scala
package rocket
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import Chisel._;
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import Node._;
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import Constants._;
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class ioUncachedRequestor extends Bundle {
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val xact_init = (new FIFOIO) { new TransactionInit }
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val xact_abort = (new FIFOIO) { new TransactionAbort }.flip
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val xact_rep = (new FIFOIO) { new TransactionReply }.flip
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val xact_finish = (new FIFOIO) { new TransactionFinish }
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}
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class rocketMemArbiter(n: Int) extends Component {
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val io = new Bundle {
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val mem = new ioUncachedRequestor
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val requestor = Vec(n) { new ioUncachedRequestor }.flip
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}
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var xi_val = Bool(false)
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var xi_rdy = io.mem.xact_init.ready
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for (i <- 0 until n)
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{
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io.requestor(i).xact_init.ready := xi_rdy
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xi_val = xi_val || io.requestor(i).xact_init.valid
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xi_rdy = xi_rdy && !io.requestor(i).xact_init.valid
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}
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var xi_bits = new TransactionInit
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xi_bits := io.requestor(n-1).xact_init.bits
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xi_bits.tile_xact_id := Cat(io.requestor(n-1).xact_init.bits.tile_xact_id, UFix(n-1, log2Up(n)))
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for (i <- n-2 to 0 by -1)
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{
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var my_xi_bits = new TransactionInit
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my_xi_bits := io.requestor(i).xact_init.bits
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my_xi_bits.tile_xact_id := Cat(io.requestor(i).xact_init.bits.tile_xact_id, UFix(i, log2Up(n)))
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xi_bits = Mux(io.requestor(i).xact_init.valid, my_xi_bits, xi_bits)
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}
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io.mem.xact_init.valid := xi_val
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io.mem.xact_init.bits := xi_bits
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var xf_val = Bool(false)
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var xf_rdy = io.mem.xact_finish.ready
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for (i <- 0 until n)
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{
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io.requestor(i).xact_finish.ready := xf_rdy
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xf_val = xf_val || io.requestor(i).xact_finish.valid
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xf_rdy = xf_rdy && !io.requestor(i).xact_finish.valid
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}
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var xf_bits = io.requestor(n-1).xact_finish.bits
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for (i <- n-2 to 0 by -1)
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xf_bits = Mux(io.requestor(i).xact_finish.valid, io.requestor(i).xact_finish.bits, xf_bits)
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io.mem.xact_finish.valid := xf_val
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io.mem.xact_finish.bits := xf_bits
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for (i <- 0 until n)
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{
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val tag = io.mem.xact_rep.bits.tile_xact_id
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io.requestor(i).xact_rep.valid := io.mem.xact_rep.valid && tag(log2Up(n)-1,0) === UFix(i)
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io.requestor(i).xact_rep.bits := io.mem.xact_rep.bits
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io.requestor(i).xact_rep.bits.tile_xact_id := tag >> UFix(log2Up(n))
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}
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for (i <- 0 until n)
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{
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val tag = io.mem.xact_abort.bits.tile_xact_id
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io.requestor(i).xact_abort.valid := io.mem.xact_abort.valid && tag(log2Up(n)-1,0) === UFix(i)
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io.requestor(i).xact_abort.bits := io.mem.xact_abort.bits
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io.requestor(i).xact_abort.bits.tile_xact_id := tag >> UFix(log2Up(n))
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}
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io.mem.xact_abort.ready := Bool(true)
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io.mem.xact_rep.ready := Bool(true)
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}
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