Quan Nguyen
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ebec444ad2
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Increase tag width for configurable precision in Hwacha
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2013-12-13 03:33:02 -08:00 |
|
Andrew Waterman
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07a91bb99a
|
Miscellaneous cleanup
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2013-12-09 19:53:14 -08:00 |
|
Andrew Waterman
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da3135ac9b
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Begin integer unit clean-up
...to make it easier to generate the superscalar version of the core.
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2013-12-09 15:06:13 -08:00 |
|
Andrew Waterman
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16d5250924
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Correct FP trap behavior on FCSR
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2013-12-05 04:18:04 -08:00 |
|
Andrew Waterman
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5814a90472
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Make DecodeLogic interface more flexible
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2013-12-05 04:16:48 -08:00 |
|
Andrew Waterman
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924261e2b2
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Update to new privileged ISA... phew
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2013-11-25 04:35:15 -08:00 |
|
Andrew Waterman
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65b8340cea
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Mitigate D$ hit -> branch -> NPC critical path
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2013-11-24 14:21:03 -08:00 |
|
Andrew Waterman
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53f726008b
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Use Mem instead of Vec[Reg] for TLB
QoR-neutral, improves simulation speed
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2013-11-24 14:21:02 -08:00 |
|
Yunsup Lee
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d450b85483
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Merge branch 'master', remote-tracking branch 'origin' into hwacha
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2013-11-21 14:57:38 -08:00 |
|
Yunsup Lee
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68e270eeb2
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fix slli/slliw encoding bug
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2013-11-21 14:44:58 -08:00 |
|
Quan Nguyen
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3b109763ad
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Connect FMA to Hwacha pipes
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2013-11-19 20:54:47 -08:00 |
|
Stephen Twigg
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a662e85f2a
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Merge branch 'master' into hwacha
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2013-11-14 16:02:44 -08:00 |
|
Yunsup Lee
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c1966e2b0a
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forgot to put htif into uncore package
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2013-11-07 15:42:03 -08:00 |
|
Yunsup Lee
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da033af0b0
|
move htif to uncore
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2013-11-07 13:18:46 -08:00 |
|
Yunsup Lee
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4c56323f6f
|
hookup all memory ports
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2013-11-05 17:12:09 -08:00 |
|
Stephen Twigg
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eae571e371
|
Remove rocc memory simplifye module (Hwacha has its own)
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2013-11-05 15:31:03 -08:00 |
|
Andrew Waterman
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12f0369e6e
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Simplify divide early out circuitry
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2013-10-29 13:20:40 -07:00 |
|
Andrew Waterman
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b44dafbdca
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Simplify branch offset mux
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2013-10-29 13:20:40 -07:00 |
|
Andrew Waterman
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23f7bab4f3
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Reduce FMA pipeline depths
FMA QoR has improved enough to allow this change.
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2013-10-29 13:20:40 -07:00 |
|
Yunsup Lee
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1583560757
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fix replay bug, don't respond when cmd is a NOP
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2013-10-28 22:35:18 -07:00 |
|
Stephen Twigg
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36b85b8ee2
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Fix issue where the MSB of D$ req tag was getting lost for all agents when an accelerator was attached.
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2013-09-25 11:51:10 -07:00 |
|
Stephen Twigg
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891e459625
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Export stats pcr register (#28 currently) to the top-level
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2013-09-25 01:16:32 -07:00 |
|
Stephen Twigg
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730a6ec76b
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AccumulatorExample now properly sets its busy bit. Also, pepper some helpful comments into AccumulatorExample
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2013-09-24 16:32:49 -07:00 |
|
Andrew Waterman
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81c752de84
|
Support disabling virtual memory
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2013-09-24 13:58:47 -07:00 |
|
Andrew Waterman
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adc386f889
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Turn off virtual memory inside RoCC base class
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2013-09-24 13:58:47 -07:00 |
|
Stephen Twigg
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3532ae0b79
|
From Andrew, actually mark scoreboard when rocc instruction with a writeback is issued. Also, fix an issue with AccumulatorExample not properly tagging its memory requests. Finally, reverted changes from f27429c to more properly follow the spike model (always return previous value of accumulator).
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2013-09-24 10:54:09 -07:00 |
|
Stephen Twigg
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db1e09f0d0
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Fix issues with RoCC AccumulatorExample stalls on memory interface
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2013-09-23 00:21:43 -07:00 |
|
Stephen Twigg
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158cee08af
|
Adjust ordering of RoCCInstruction to reflect new ISA encoding. (Note: Fixes register op issues with AccumulatorExample but still slight issue with executing memory loads)
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2013-09-22 03:18:06 -07:00 |
|
Andrew Waterman
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1d2f4f8437
|
New ISA encoding, AUIPC semantics
|
2013-09-21 06:32:40 -07:00 |
|
Andrew Waterman
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25ab402932
|
swap JAL, JALR encodings
|
2013-09-15 04:29:06 -07:00 |
|
Andrew Waterman
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110e53cb48
|
Revert "Add early out to multiplier"
This broke recently and I don't have time to figure out why.
|
2013-09-15 04:15:32 -07:00 |
|
Andrew Waterman
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88d1c47665
|
don't disassemble within chisel
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2013-09-15 04:14:45 -07:00 |
|
Andrew Waterman
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f12bbc1e43
|
working RoCC AccumulatorExample
|
2013-09-14 22:34:53 -07:00 |
|
Andrew Waterman
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18968dfbc7
|
Move store data generation into cache
|
2013-09-14 16:15:07 -07:00 |
|
Andrew Waterman
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a0cb711451
|
Start adding RoCC
|
2013-09-14 15:31:50 -07:00 |
|
Andrew Waterman
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d053bdc89f
|
Remove Hwacha from Rocket
Soon it will use the coprocessor interface.
|
2013-09-12 22:34:38 -07:00 |
|
Andrew Waterman
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1edb1e2a0a
|
Ignore LSB of PC
|
2013-09-12 17:55:58 -07:00 |
|
Andrew Waterman
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59f5358435
|
Implement AQ/RL; move fence logic out of cache
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2013-09-12 16:07:30 -07:00 |
|
Andrew Waterman
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243c4ae342
|
sync up rocket with new isa
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2013-09-12 03:44:38 -07:00 |
|
Andrew Waterman
|
95dd0d8be1
|
Remove DebugIO/error mode
|
2013-09-11 20:15:21 -07:00 |
|
Henry Cook
|
f9b85d8158
|
NetworkIOs no longer use thunks
|
2013-09-10 16:15:19 -07:00 |
|
Henry Cook
|
d06e24ac24
|
new enum syntax
|
2013-09-10 10:51:35 -07:00 |
|
Stephen Twigg
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cfbfa6b895
|
Add errors due to merge issues. Note, DebugIO re-introduced here but slated for possible removal in later commits.
|
2013-09-05 19:22:34 -07:00 |
|
Stephen Twigg
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d896ccbd43
|
Merge branch 'master' into chisel-v2
Conflicts:
src/main/scala/htif.scala
|
2013-09-05 16:11:53 -07:00 |
|
Andrew Waterman
|
b9f6e1a7ec
|
Don't update BTB when garbage was fetched
|
2013-08-26 14:53:04 -07:00 |
|
Yunsup Lee
|
44e92edf92
|
fix scr parameterization bug
|
2013-08-24 22:42:51 -07:00 |
|
Andrew Waterman
|
3895b75a56
|
Support non-power-of-2 BTBs; prefer invalid entries
|
2013-08-24 17:33:11 -07:00 |
|
Yunsup Lee
|
2ca5127785
|
parameterize number of SCRs
|
2013-08-24 15:47:14 -07:00 |
|
Andrew Waterman
|
daf23b8f79
|
Add early out to multiplier
|
2013-08-24 14:44:23 -07:00 |
|
Andrew Waterman
|
67f80ba4b2
|
Stall div/mul writeback until WB slot is free
|
2013-08-24 14:44:17 -07:00 |
|