Andrew Waterman
|
18968dfbc7
|
Move store data generation into cache
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2013-09-14 16:15:07 -07:00 |
|
Andrew Waterman
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a0cb711451
|
Start adding RoCC
|
2013-09-14 15:31:50 -07:00 |
|
Andrew Waterman
|
d053bdc89f
|
Remove Hwacha from Rocket
Soon it will use the coprocessor interface.
|
2013-09-12 22:34:38 -07:00 |
|
Andrew Waterman
|
1edb1e2a0a
|
Ignore LSB of PC
|
2013-09-12 17:55:58 -07:00 |
|
Andrew Waterman
|
fbdbb01232
|
update to new isa; disable vector tests
|
2013-09-12 17:04:03 -07:00 |
|
Andrew Waterman
|
cc7783404d
|
Add memory command M_XA_XOR
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2013-09-12 16:09:53 -07:00 |
|
Andrew Waterman
|
59f5358435
|
Implement AQ/RL; move fence logic out of cache
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2013-09-12 16:07:30 -07:00 |
|
Andrew Waterman
|
243c4ae342
|
sync up rocket with new isa
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2013-09-12 03:44:38 -07:00 |
|
Andrew Waterman
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95dd0d8be1
|
Remove DebugIO/error mode
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2013-09-11 20:15:21 -07:00 |
|
Henry Cook
|
b42e140e05
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NetworkIOs no longer use thunks
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2013-09-10 16:23:52 -07:00 |
|
Henry Cook
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1cac26fd76
|
NetworkIOs no longer use thunks
|
2013-09-10 16:15:41 -07:00 |
|
Henry Cook
|
f9b85d8158
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NetworkIOs no longer use thunks
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2013-09-10 16:15:19 -07:00 |
|
Henry Cook
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ee98cd8378
|
new enum syntax
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2013-09-10 10:54:51 -07:00 |
|
Henry Cook
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d06e24ac24
|
new enum syntax
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2013-09-10 10:51:35 -07:00 |
|
Stephen Twigg
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6cde69e95d
|
Merge changes from master. This updates rocket more than it should so while the emulator builds, programs will not execute correctly due to ISA changes, etc.
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2013-09-09 14:31:18 -07:00 |
|
Stephen Twigg
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cfbfa6b895
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Add errors due to merge issues. Note, DebugIO re-introduced here but slated for possible removal in later commits.
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2013-09-05 19:22:34 -07:00 |
|
Stephen Twigg
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e23e8e3850
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Merge branch 'master' into chisel-v2
Conflicts:
src/main/scala/memserdes.scala
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2013-09-05 16:17:34 -07:00 |
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Stephen Twigg
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d896ccbd43
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Merge branch 'master' into chisel-v2
Conflicts:
src/main/scala/htif.scala
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2013-09-05 16:11:53 -07:00 |
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Stephen Twigg
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f27c0fb010
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Merge commit '2bd4a66eee572252ba6250f9bddada51657fc379' into chisel-v2
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2013-09-05 15:01:56 -07:00 |
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Stephen Twigg
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69daae0dae
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Add dependency resolvers to build.scala to fix build script
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2013-09-05 14:56:41 -07:00 |
|
Yunsup Lee
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2c47b4388a
|
push rocket
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2013-08-26 14:54:49 -07:00 |
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Andrew Waterman
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b9f6e1a7ec
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Don't update BTB when garbage was fetched
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2013-08-26 14:53:04 -07:00 |
|
Yunsup Lee
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9003bc2614
|
push rocket
|
2013-08-24 22:42:57 -07:00 |
|
Yunsup Lee
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44e92edf92
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fix scr parameterization bug
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2013-08-24 22:42:51 -07:00 |
|
Yunsup Lee
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d0674af13f
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forgot to push riscv-rocket
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2013-08-24 22:15:38 -07:00 |
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Andrew Waterman
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3895b75a56
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Support non-power-of-2 BTBs; prefer invalid entries
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2013-08-24 17:33:11 -07:00 |
|
Yunsup Lee
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ba9bbc27df
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apply same change to fpga top-level
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2013-08-24 15:50:03 -07:00 |
|
Yunsup Lee
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76cd90fc01
|
parameterize number of SCRs
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2013-08-24 15:47:42 -07:00 |
|
Yunsup Lee
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2ca5127785
|
parameterize number of SCRs
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2013-08-24 15:47:14 -07:00 |
|
Yunsup Lee
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694ebd65cf
|
push uncore
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2013-08-24 15:24:25 -07:00 |
|
Yunsup Lee
|
b01fe4f6aa
|
fix memserdes bit ordering
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2013-08-24 15:24:17 -07:00 |
|
Andrew Waterman
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daf23b8f79
|
Add early out to multiplier
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2013-08-24 14:44:23 -07:00 |
|
Andrew Waterman
|
67f80ba4b2
|
Stall div/mul writeback until WB slot is free
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2013-08-24 14:44:17 -07:00 |
|
Andrew Waterman
|
d1b5076fee
|
Don't update BTB when garbage was fetched
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2013-08-24 14:44:11 -07:00 |
|
Andrew Waterman
|
52e31f3298
|
Bypass scoreboard updates
This reduces div/mul/D$ miss latency by 1 cycle.
|
2013-08-24 14:44:04 -07:00 |
|
Andrew Waterman
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d4a0db4575
|
Reflect ISA changes
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2013-08-24 14:43:55 -07:00 |
|
Yunsup Lee
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0884bc9789
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fix DRAMSideLLCNull entries
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2013-08-24 13:20:38 -07:00 |
|
Yunsup Lee
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1e3ac0afa9
|
back to NTILES=1
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2013-08-24 13:10:30 -07:00 |
|
Henry Cook
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9aff60f340
|
whitespace error in build.sbt
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2013-08-21 16:16:42 -07:00 |
|
Henry Cook
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dc53529156
|
added resolver, bumped chisel dependency
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2013-08-21 16:00:51 -07:00 |
|
Henry Cook
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6aa500fc16
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dont make assumptions about default project name when invoking sbt
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2013-08-20 12:56:01 -07:00 |
|
Henry Cook
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b06d33da2f
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Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes
|
2013-08-19 19:54:41 -07:00 |
|
Henry Cook
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ff7b486006
|
standardized sbt build
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2013-08-15 18:13:19 -07:00 |
|
Henry Cook
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85e5ce046f
|
pulled submodule commits, uncore sbt standardized
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2013-08-15 17:07:13 -07:00 |
|
Henry Cook
|
6b20556661
|
Merge branch 'chisel-v2' of github.com:ucb-bar/reference-chip into chisel-v2
Conflicts:
chisel
riscv-hwacha
riscv-rocket
uncore
|
2013-08-15 16:39:30 -07:00 |
|
Henry Cook
|
784e017bae
|
Final Reg standardization
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2013-08-15 16:37:58 -07:00 |
|
Henry Cook
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ae02ebd153
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Merge branch 'chisel-v2' of github.com:ucb-bar/riscv-rocket into chisel-v2
Conflicts:
src/core.scala
src/ctrl.scala
src/dpath_util.scala
src/fpu.scala
src/nbdcache.scala
src/tile.scala
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2013-08-15 16:35:27 -07:00 |
|
Henry Cook
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b80f45f8f2
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Merge branch 'chisel-v2' of github.com:ucb-bar/uncore into chisel-v2
Conflicts:
src/main/scala/llc.scala
src/main/scala/slowio.scala
|
2013-08-15 16:22:12 -07:00 |
|
Henry Cook
|
3763cd0004
|
standardizing sbt build conventions
|
2013-08-15 15:57:16 -07:00 |
|
Henry Cook
|
3a266cbbfa
|
final Reg changes
|
2013-08-15 15:28:15 -07:00 |
|