riscv/rocket-chip
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Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)
120 Commits 1 Branch 0 Tags 13 MiB
Scala 93.1%
C++ 2.1%
Python 2%
Makefile 1.2%
Verilog 0.8%
Other 0.7%
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Henry Cook 6b20556661 Merge branch 'chisel-v2' of github.com:ucb-bar/reference-chip into chisel-v2 
Conflicts:
	chisel
	riscv-hwacha
	riscv-rocket
	uncore
2013-08-15 16:39:30 -07:00
chisel@8eb2d8a20d Merge branch 'chisel-v2' of github.com:ucb-bar/reference-chip into chisel-v2 2013-08-15 16:39:30 -07:00
csrc Use chisel printf for logging 2013-06-13 10:53:23 -07:00
dramsim2@0b3ee6799a integrate updated rocket/uncore 2012-10-18 17:51:41 -07:00
emulator require -std=c++11, as -std=c++0x doesn't cut it 2013-06-14 00:28:42 -07:00
hardfloat@76ac1cb932 initial attempt at upgrade 2013-08-12 10:46:22 -07:00
project Bump scala to 2.10.2, sbt to 0.13-RC2, including new launcher. Upgrade reflection in network.scala to 2.10 lib. Constants now obtained from subproject package objects. Give network its own file. 2013-07-24 23:28:43 -07:00
riscv-rocket@4461c5f4ed Merge branch 'chisel-v2' of github.com:ucb-bar/reference-chip into chisel-v2 2013-08-15 16:39:30 -07:00
riscv-tests@c31d7c5eb4 removed bad mt test 2013-06-14 00:14:18 -07:00
riscv-tools@4806a4a74e Updated riscv-tools reference 2013-07-10 16:01:01 -07:00
src/main/scala Merge branch 'chisel-v2' of github.com:ucb-bar/reference-chip into chisel-v2 2013-08-15 16:39:30 -07:00
uncore@4a8bb15978 Merge branch 'chisel-v2' of github.com:ucb-bar/reference-chip into chisel-v2 2013-08-15 16:39:30 -07:00
.gitmodules add submodule riscv-tools 2013-05-10 11:53:55 -07:00
Makefrag removed bad mt test 2013-06-14 00:14:18 -07:00
README update README 2013-05-13 11:19:55 -07:00
sbt-launch.jar Bump scala to 2.10.2, sbt to 0.13-RC2, including new launcher. Upgrade reflection in network.scala to 2.10 lib. Constants now obtained from subproject package objects. Give network its own file. 2013-07-24 23:28:43 -07:00

README 

Quick and dirty instructions:

CHECKOUT THE CODE:

  git submodule update --init

  cd riscv-tools
  git submodule update --init


BUILDING THE TOOLCHAIN:

  To build RISC-V ISA simulator, frontend server, proxy kernel and newlib based GNU toolchain:

    export RISCV=/path/to/riscv/toolchain/installation
    cd riscv-tools
    ./build.sh

  To build asm tests and benchmarks (you must have the RISC-V toolchain installed and in your path):

    cd riscv-tests/isa/
    make -j

    cd riscv-tests/benchmarks
    make -j

BUILDING THE PROJECT:

  To build the C simulator:

    cd emulator
    make

  To build the VCS simulator:

    cd vlsi/build/vcs-sim-rtl
    make

  in either case, you can run a set of assembly tests or simple benchmarks:

    make run-asm-tests
    make run-vecasm-tests
    make run-vecasm-timer-tests
    make run-bmarks-test

  To build a C simulator that is capable of VCD waveform generation:

    cd emulator
    make emulator-debug

  And to run the assembly tests on the C simulator and generate waveforms:

    make run-asm-tests-debug
    make run-vecasm-tests-debug
    make run-vecasm-timer-tests-debug
    make run-bmarks-test-debug


UPDATING TO A NEWER VERSION OF CHISEL:

  To grab a newer version of chisel:

    git submodule update --init
    cd chisel
    git pull origin master

  Then, to compile it and install it into the rocket repo:

    cd sbt
    sbt package
    cp chisel/target/scala-2.8.1/chisel_2.8.1-1.1.jar ../../sbt/work/lib

  If you commit a new jar, you must also commit the updated chisel submodule.