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Commit Graph

823 Commits

Author SHA1 Message Date
3d35ccd401 Explicitely convert results of Bits Muxes to UInt
Chisel updated to emit SInt result instead of UInt so this commit addresses this change.
2015-02-03 18:10:54 -08:00
741e6b77ad Rename some params, use refactored TileLink 2015-02-01 20:37:31 -08:00
00e074cdd9 fixes slight bug for non-power of 2 number of ras entries 2015-01-29 15:29:25 -08:00
a98127c09e Merge branch 'ss-frontend' 2015-01-04 20:26:38 -08:00
b70f7683d3 Merge branch 'master' into ss-frontend
Conflicts:
	src/main/scala/ctrl.scala
2015-01-04 19:59:18 -08:00
87ad1a5703 More control cleanup 2015-01-04 19:46:01 -08:00
2aee85cb11 Flush pipeline from MEM stage
This means we no longer have to rely on the instruction behind a serializing
instruction being valid, simplifying the control.  But we have to be a
little more cautious when flusing the I$/ITLB/BTB.
2015-01-04 16:40:16 -08:00
94b75c7cb1 Continue refactoring control 2015-01-04 15:32:05 -08:00
6181de4cc9 Much refactor, so control 2015-01-03 13:34:38 -08:00
1cb65d5ec1 %s/master/manager/g 2014-12-29 22:56:18 -08:00
77e5e6b561 refill bug 2014-12-17 19:29:28 -08:00
08dcf4c6ca refactor cache params 2014-12-17 14:28:05 -08:00
d29793d1f7 cleanup CoherenceMetadata and coherence params 2014-12-15 19:23:38 -08:00
c9320862ae add l2 dmem signal to rocc 2014-12-12 16:55:08 -08:00
72ea24283b multibeat TL; passes all tests 2014-12-12 16:54:33 -08:00
f19b3ca43e Deleted extra spaces at EOL in ctrl.scala 2014-11-16 22:04:33 -08:00
6749f67b7f Fixed BHT update error.
- separated out BTB/BHT update
   - BHT updates counters on every branch
   - BTB update only on mispredicted and taken branches
2014-11-16 22:02:27 -08:00
b7b2923bff Cleanup MSHR internal bundles 2014-11-11 18:18:35 -08:00
c9e7874818 Major tilelink revision for uncached message types 2014-11-11 17:36:48 -08:00
fea31d2167 Significant changes and fixes to BTB for superscalar fetch.
- BTBUpdate only occurs on mispredicts now.
   - RASUpdate broken out from BTBUpdate (allows RASUpdate to be performed in
      Decode).
   - Added optional 2nd CAM port to BTB for updates (for when updates to the
      BTB may occur out-of-order).
   - Fixed resp.mask bit logic.
2014-11-11 03:34:05 -08:00
bf901e4bca Remove master_xact_id from Release 2014-11-06 12:09:45 -08:00
3be3cd7731 Fixed error with icache/btb resp mask. 2014-11-03 01:13:22 -08:00
08d2c13330 Fixed btb/icache bugs regarding resp mask, fw==1 2014-10-20 18:45:23 -07:00
91efdc379b Merge remote-tracking branch 'origin/master' into ss-frontend
Also fixed bridx logic and zero-width wire logic.

Conflicts:
	src/main/scala/btb.scala
2014-10-14 18:10:29 -07:00
7bb7299018 Don't pollute BTB with PC+4 target predictions 2014-10-14 17:28:37 -07:00
59eb7d194d Finalize superscalar btb. 2014-10-03 16:08:08 -07:00
cde7c9d869 simplify CSR decoding code 2014-10-03 14:31:26 -07:00
99614e37aa Merge remote-tracking branch 'origin/master' into ss-frontend
Conflicts:
	src/main/scala/btb.scala
	src/main/scala/core.scala
2014-10-03 04:22:58 -07:00
9cc35dee9a Returned history update to fetch.
- Global history only contains branches.
   - Only update BHT and history on BTB hits.
   - Gate off speculative update on stall or icmiss.
   - Fixed bug where BHT updates were delayed a cycle.
2014-09-29 21:41:07 -07:00
8ccd07cfeb Moved updating global history from fetch to decode.
- No longer update global history in fetch stage.
   - Only update global history when instruction is a branch.
   - Does allow for the possibility of back-to-back branches to see
     slightly different histories on subsequent executions.
2014-09-28 05:16:36 -07:00
681b43f398 Bug fixes with global history register.
- Updated in fetch speculatively.
      * Updates gated off by cpu.resp.fire().
      * BTB direction factored into history update.
   - All branches update the BHT.
   - Each instruction carries history; index into BHT is recomputed by
     passing in mem_reg_pc.
2014-09-26 10:39:57 -07:00
a71bdbbc54 Update history register in fetch speculatively 2014-09-26 05:42:08 -07:00
f917810061 Removed RocketCoreParameters from use.
- The nbdache (among others?) use CoreParameters, which has nothing to do with RetireWidth requirements.
   - This conflicts with other cores which uses nbdcache.
   - RocketCoreParameters may be unneccessary, and the require() check can be moved deeper into Rocket.
2014-09-26 05:14:50 -07:00
868e747656 Factored out Rocket specifics from CoreParameters
- Added new RocketCoreParameters
   - Other cores using Rocket as a library will no longer conflict against
      Rocket's requires().
2014-09-25 18:52:58 -07:00
8eb64205f5 bug fix for nbdcache s2_data 2014-09-25 12:00:20 -07:00
b55c38cdc7 Remove spurious vec consts 2014-09-25 12:00:20 -07:00
3e256439c9 Add abstract class Tile 2014-09-24 13:04:20 -07:00
180d3d365d Expanded front-end to support superscalar fetch. 2014-09-17 14:24:03 -07:00
238f7761f6 update README 2014-09-17 11:23:25 -07:00
8abf62fae3 add LICENSE 2014-09-12 18:06:41 -07:00
25180b71f7 add LICENSE 2014-09-12 15:36:42 -07:00
a999c055ed Don't take an interrupt when EX stage PC is invalid
It was possible to take an interrupt on the instruction in the shadow of
a short forward branch.  EPC would thus get the wrong value, and so
a wrong-path instruction would be executed upon return from interrupt.

h/t Yunsup
2014-09-11 01:46:52 -07:00
5eb5e9eaf5 Standardize ()=>Module(...) top-level Parameters 2014-09-07 17:54:41 -07:00
5e2f98747f Merge branch 'dse' 2014-09-06 06:10:15 -07:00
600c5d50a9 better fix with explanation of sbt issue 2014-09-02 15:14:56 -07:00
f9922a106b fixes sbt error during first run 2014-09-02 14:34:36 -07:00
b42a2ab40a Final parameter refactor 2014-09-01 13:28:58 -07:00
2d6aafc32e Merge branch 'dse' of github.com:ucb-bar/rocket-staging into HEAD 2014-09-01 11:23:50 -07:00
83c6c2c9e2 rename refs to zynq-fpga to fpga-zynq 2014-08-29 10:26:48 -07:00
6a4193cf90 minor cache param cleanup 2014-08-19 11:38:46 -07:00