riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
853 Commits 1 Branch 0 Tags 13 MiB
2f88c5ca9d
Commit Graph

842 Commits

Author SHA1 Message Date
Andrew Waterman
09e2ec1f9e Fix sign of remainder when dividing by zero 
h/t chris
 2014-04-18 16:32:57 -07:00
Henry Cook
1fa505f9ff remove superfluous AVec object 2014-04-16 17:19:32 -07:00
Andrew Waterman
3520620fbd Remove D$ -> BTB path 2014-04-15 23:05:02 -07:00
Andrew Waterman
de492b3cf7 Fix critical path through integer scoreboard 2014-04-15 21:28:13 -07:00
Henry Cook
444d0449e3 io.cnt bug in serializer 2014-04-14 17:13:13 -07:00
Henry Cook
1da8ef2ddf Added serdes to decouple cache row size from tilelink data size 2014-04-10 12:34:12 -07:00
Henry Cook
910b3b203a removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants 2014-04-10 12:32:44 -07:00
Henry Cook
ebdc0a2692 merge Aqcuire and AcquireData. cache line size coupled to tilelink data size 2014-04-10 12:09:52 -07:00
Stephen Twigg
e90f2484aa Sync with riscv-opcodes (csr register mapping) 2014-04-08 15:48:37 -07:00
Andrew Waterman
3ed8adf032 Add early out for MUL[W] (not MULH[[S]U]) 2014-04-07 23:48:02 -07:00
Andrew Waterman
927287da34 Bypass RAS push/pop 2014-04-07 23:47:53 -07:00
Andrew Waterman
f235fa0db6 Move branch resolution to M stage 2014-04-07 15:58:49 -07:00
Andrew Waterman
db59fc65ab Add return address stack 2014-04-01 15:01:27 -07:00
Andrew Waterman
e3b12e0b85 Make BTB more complexity-effective 
BTB entries reference a small number of unique pages, so we separate the
storage of pages from indices.  This makes much larger BTBs feasible.  It's
easy to exacerbate cycle time this way, so one-hot encoding is used as needed.
 2014-03-25 05:22:04 -07:00
Andrew Waterman
804b09c8c5 Frontend QoR tweaks 2014-03-25 05:20:24 -07:00
Andrew Waterman
6465e2df14 Make Int -> Bool conversions explicit 2014-03-24 04:36:53 -07:00
Andrew Waterman
1b030777ce Remove vestigial control signal 2014-03-24 04:36:12 -07:00
Andrew Waterman
5996418021 Fix exception behavior of fmin/fmax 2014-03-18 18:36:51 -07:00
Andrew Waterman
54cbf0c4f1 Add (unused) RV32 CSRs 2014-03-15 17:33:17 -07:00
Andrew Waterman
943d7ac80a Use LinkedHashSet/Map for simpler determinism 2014-03-15 17:31:48 -07:00
Donggyu Kim
53d62cb69d remove nondeterminism 2014-03-15 16:45:58 -07:00
Andrew Waterman
a0389645b7 New FP encoding; improved FP implementation 2014-03-11 18:58:24 -07:00
Andrew Waterman
00bc1a2293 Add fclass.{s|d} instructions 2014-03-10 16:59:24 -07:00
Yunsup Lee
ac4b3f9f22 print out core id 2014-03-04 23:38:49 -08:00
Andrew Waterman
9f2e16c58a Fix D$ arbiter for >2 inputs 2014-03-04 16:32:17 -08:00
Andrew Waterman
fa75f6e81e Fix null pointer exception when HAS_FPU=false 2014-03-04 16:32:09 -08:00
Andrew Waterman
c7110c8389 Make FPU pipeline depths configurable 2014-02-28 13:39:59 -08:00
Yunsup Lee
98b830201a add wen signal to dasm printf 2014-02-25 03:31:06 -08:00
Yunsup Lee
97b1841fcf change dcache tag bits to 7 2014-02-22 22:53:04 -08:00
Andrew Waterman
8e3ca609f7 Renumber uarch CSRs into custom CSR space 2014-02-14 17:40:00 -08:00
Andrew Waterman
a09ff9fdc7 Revert to old AUIPC definition 2014-02-10 19:04:42 -08:00
Andrew Waterman
1456170c6d Always stall decode on RoCC -> FENCE; never stall on RoCC -> deferred AMO.RL fence 2014-02-06 12:01:49 -08:00
Andrew Waterman
eca8c99f44 Ignore rocc interrupt line when no rocc is present 2014-02-06 03:06:55 -08:00
Andrew Waterman
e7a726fbac Make uarch counters read-only 2014-02-06 01:48:56 -08:00
Quan Nguyen
f021213b1d Merge remote-tracking branch 'origin/master' into hwacha-port 2014-02-06 00:21:28 -08:00
Andrew Waterman
62e9313aef Add 16 microarchitectural counters 2014-02-06 00:13:02 -08:00
Yunsup Lee
ff7cae29f7 hookup rocc interrupt and s bit 2014-02-06 00:09:42 -08:00
Yunsup Lee
ab4a3e937b don't share fma pipes 2014-02-05 14:21:43 -08:00
Stephen Twigg
6a02d15c21 Merge branch 'master' into hwacha-port 2014-02-04 17:05:03 -08:00
Henry Cook
2c2b3a7678 cleanups supporting uncore hierarchy 2014-01-31 12:07:26 -08:00
Andrew Waterman
febd26f505 Correct CSR privilege logic 2014-01-31 01:03:17 -08:00
Stephen Twigg
3c3c469725 Add exception signal to rocc interface 2014-01-28 22:13:16 -08:00
Andrew Waterman
0266c1f76a Support retirement width > 1 in CSR file 2014-01-24 16:37:40 -08:00
Andrew Waterman
267394d3cc Fix CSR interlocks 2014-01-24 16:37:40 -08:00
Andrew Waterman
1f986d1c96 Branches don't care about the ALU input/function 2014-01-24 16:37:40 -08:00
Andrew Waterman
a1b7774f5d Simplify handling of CAUSE register 2014-01-24 16:37:39 -08:00
Christopher Celio
a2be21361e Allow ICacheConfig to toggle fetch-width. 2014-01-22 16:19:57 -08:00
Andrew Waterman
a7489920ce Support CSR atomics on all CSRs, not just STATUS 2014-01-21 16:17:39 -08:00
Andrew Waterman
6ba2c1abe5 Use auto-generated CAUSE constants 2014-01-21 15:01:54 -08:00
Andrew Waterman
95de358a96 More of the same FPU fix 
some SP ops followed by DP stores were not working because they
were encoded as subnormals, not NaNs.
 2014-01-17 14:09:30 -08:00
Andrew Waterman
cf38001e98 Fix fmv.s.x -> fsd 2014-01-17 03:52:35 -08:00
Yunsup Lee
30b894c2c4 Merge remote-tracking branch 'origin/master' into hwacha-port 2014-01-16 16:04:48 -08:00
Yunsup Lee
6bbbf36979 push accel/rocket dmem port back to rocket 2014-01-16 16:01:41 -08:00
Andrew Waterman
57f4d89c90 Generate D$ replay_next signals correctly 2014-01-16 00:16:09 -08:00
Andrew Waterman
6ebdc4d94e Simplify store conditional failure code generation 2014-01-16 00:15:48 -08:00
Andrew Waterman
31060ea8ae Fix fubar long-latency writeback control logic 
Load miss writebacks happening at the same time as multiplication
wasn't working.  Hopefully this does it.
 2014-01-14 04:02:43 -08:00
Andrew Waterman
e8486817e6 Clean up formatting (i.e. remove tabs, semicolons) 2014-01-13 21:43:56 -08:00
Andrew Waterman
a50a1f7d50 Clean up multiplier/divider stuff 2014-01-13 21:37:16 -08:00
Andrew Waterman
4d236979bd Fix very far forward JALs 
We were sign-extending from the wrong bit, causing a backwards jump.
 2014-01-13 00:55:48 -08:00
Andrew Waterman
c546f66404 Swap JAL/JALR encodings (again) 2014-01-13 00:54:49 -08:00
Quan Nguyen
ebec444ad2 Increase tag width for configurable precision in Hwacha 2013-12-13 03:33:02 -08:00
Andrew Waterman
07a91bb99a Miscellaneous cleanup 2013-12-09 19:53:14 -08:00
Andrew Waterman
da3135ac9b Begin integer unit clean-up 
...to make it easier to generate the superscalar version of the core.
 2013-12-09 15:06:13 -08:00
Andrew Waterman
16d5250924 Correct FP trap behavior on FCSR 2013-12-05 04:18:04 -08:00
Andrew Waterman
5814a90472 Make DecodeLogic interface more flexible 2013-12-05 04:16:48 -08:00
Andrew Waterman
924261e2b2 Update to new privileged ISA... phew 2013-11-25 04:35:15 -08:00
Andrew Waterman
65b8340cea Mitigate D$ hit -> branch -> NPC critical path 2013-11-24 14:21:03 -08:00
Andrew Waterman
53f726008b Use Mem instead of Vec[Reg] for TLB 
QoR-neutral, improves simulation speed
 2013-11-24 14:21:02 -08:00
Yunsup Lee
d450b85483 Merge branch 'master', remote-tracking branch 'origin' into hwacha 2013-11-21 14:57:38 -08:00
Yunsup Lee
68e270eeb2 fix slli/slliw encoding bug 2013-11-21 14:44:58 -08:00
Quan Nguyen
3b109763ad Connect FMA to Hwacha pipes 2013-11-19 20:54:47 -08:00
Stephen Twigg
a662e85f2a Merge branch 'master' into hwacha 2013-11-14 16:02:44 -08:00
Yunsup Lee
c1966e2b0a forgot to put htif into uncore package 2013-11-07 15:42:03 -08:00
Yunsup Lee
da033af0b0 move htif to uncore 2013-11-07 13:18:46 -08:00
Yunsup Lee
4c56323f6f hookup all memory ports 2013-11-05 17:12:09 -08:00
Stephen Twigg
eae571e371 Remove rocc memory simplifye module (Hwacha has its own) 2013-11-05 15:31:03 -08:00
Andrew Waterman
12f0369e6e Simplify divide early out circuitry 2013-10-29 13:20:40 -07:00
Andrew Waterman
b44dafbdca Simplify branch offset mux 2013-10-29 13:20:40 -07:00
Andrew Waterman
23f7bab4f3 Reduce FMA pipeline depths 
FMA QoR has improved enough to allow this change.
 2013-10-29 13:20:40 -07:00
Yunsup Lee
1583560757 fix replay bug, don't respond when cmd is a NOP 2013-10-28 22:35:18 -07:00
Stephen Twigg
36b85b8ee2 Fix issue where the MSB of D$ req tag was getting lost for all agents when an accelerator was attached. 2013-09-25 11:51:10 -07:00
Stephen Twigg
891e459625 Export stats pcr register (#28 currently) to the top-level 2013-09-25 01:16:32 -07:00
Stephen Twigg
730a6ec76b AccumulatorExample now properly sets its busy bit. Also, pepper some helpful comments into AccumulatorExample 2013-09-24 16:32:49 -07:00
Andrew Waterman
81c752de84 Support disabling virtual memory 2013-09-24 13:58:47 -07:00
Andrew Waterman
adc386f889 Turn off virtual memory inside RoCC base class 2013-09-24 13:58:47 -07:00
Stephen Twigg
3532ae0b79 From Andrew, actually mark scoreboard when rocc instruction with a writeback is issued. Also, fix an issue with AccumulatorExample not properly tagging its memory requests. Finally, reverted changes from f27429c to more properly follow the spike model (always return previous value of accumulator). 2013-09-24 10:54:09 -07:00
Stephen Twigg
db1e09f0d0 Fix issues with RoCC AccumulatorExample stalls on memory interface 2013-09-23 00:21:43 -07:00
Stephen Twigg
158cee08af Adjust ordering of RoCCInstruction to reflect new ISA encoding. (Note: Fixes register op issues with AccumulatorExample but still slight issue with executing memory loads) 2013-09-22 03:18:06 -07:00
Andrew Waterman
1d2f4f8437 New ISA encoding, AUIPC semantics 2013-09-21 06:32:40 -07:00
Andrew Waterman
25ab402932 swap JAL, JALR encodings 2013-09-15 04:29:06 -07:00
Andrew Waterman
110e53cb48 Revert "Add early out to multiplier" 
This broke recently and I don't have time to figure out why.
 2013-09-15 04:15:32 -07:00
Andrew Waterman
88d1c47665 don't disassemble within chisel 2013-09-15 04:14:45 -07:00
Andrew Waterman
f12bbc1e43 working RoCC AccumulatorExample 2013-09-14 22:34:53 -07:00
Andrew Waterman
18968dfbc7 Move store data generation into cache 2013-09-14 16:15:07 -07:00
Andrew Waterman
a0cb711451 Start adding RoCC 2013-09-14 15:31:50 -07:00
Andrew Waterman
d053bdc89f Remove Hwacha from Rocket 
Soon it will use the coprocessor interface.
 2013-09-12 22:34:38 -07:00
Andrew Waterman
1edb1e2a0a Ignore LSB of PC 2013-09-12 17:55:58 -07:00
Andrew Waterman
59f5358435 Implement AQ/RL; move fence logic out of cache 2013-09-12 16:07:30 -07:00
Andrew Waterman
243c4ae342 sync up rocket with new isa 2013-09-12 03:44:38 -07:00
Andrew Waterman
95dd0d8be1 Remove DebugIO/error mode 2013-09-11 20:15:21 -07:00
Henry Cook
f9b85d8158 NetworkIOs no longer use thunks 2013-09-10 16:15:19 -07:00
Henry Cook
d06e24ac24 new enum syntax 2013-09-10 10:51:35 -07:00
Stephen Twigg
cfbfa6b895 Add errors due to merge issues. Note, DebugIO re-introduced here but slated for possible removal in later commits. 2013-09-05 19:22:34 -07:00
Stephen Twigg
d896ccbd43 Merge branch 'master' into chisel-v2 
Conflicts:
	src/main/scala/htif.scala
 2013-09-05 16:11:53 -07:00
Andrew Waterman
b9f6e1a7ec Don't update BTB when garbage was fetched 2013-08-26 14:53:04 -07:00
Yunsup Lee
44e92edf92 fix scr parameterization bug 2013-08-24 22:42:51 -07:00
Andrew Waterman
3895b75a56 Support non-power-of-2 BTBs; prefer invalid entries 2013-08-24 17:33:11 -07:00
Yunsup Lee
2ca5127785 parameterize number of SCRs 2013-08-24 15:47:14 -07:00
Andrew Waterman
daf23b8f79 Add early out to multiplier 2013-08-24 14:44:23 -07:00
Andrew Waterman
67f80ba4b2 Stall div/mul writeback until WB slot is free 2013-08-24 14:44:17 -07:00
Andrew Waterman
d1b5076fee Don't update BTB when garbage was fetched 2013-08-24 14:44:11 -07:00
Andrew Waterman
52e31f3298 Bypass scoreboard updates 
This reduces div/mul/D$ miss latency by 1 cycle.
 2013-08-24 14:44:04 -07:00
Andrew Waterman
d4a0db4575 Reflect ISA changes 2013-08-24 14:43:55 -07:00
Henry Cook
ff7b486006 standardized sbt build 2013-08-15 18:13:19 -07:00
Henry Cook
ae02ebd153 Merge branch 'chisel-v2' of github.com:ucb-bar/riscv-rocket into chisel-v2 
Conflicts:
	src/core.scala
	src/ctrl.scala
	src/dpath_util.scala
	src/fpu.scala
	src/nbdcache.scala
	src/tile.scala
 2013-08-15 16:35:27 -07:00
Henry Cook
3a266cbbfa final Reg changes 2013-08-15 15:28:15 -07:00
Henry Cook
b570435847 Reg standardization 2013-08-13 17:50:02 -07:00
Henry Cook
858169917e removed dummy DNCs handled by pruning 2013-08-12 22:34:46 -07:00
Henry Cook
d9b3c7cfc8 Moved RenEn to ChiselUtil 2013-08-12 22:18:25 -07:00
Huy Vo
387cf0ebe0 reset -> resetVal, getReset -> reset 2013-08-12 20:51:54 -07:00
Henry Cook
1a9e43aa11 initial attempt at upgrade 2013-08-12 10:39:11 -07:00
Henry Cook
de313d97de Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2013-08-02 16:30:09 -07:00
Henry Cook
4eaab214d2 Fold uncore constants into TileLinkConfiguration, update coherence API 2013-08-02 16:29:51 -07:00
Henry Cook
bef6c1db35 minor nbdcache cleanup 2013-08-02 16:29:37 -07:00
Stephen Twigg
3132db4f90 Add stats PCR (cr28) to be used to flag whether a core is doing 'interesting' activity. 2013-07-30 16:36:28 -07:00
Henry Cook
9abdf4e154 Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object. 2013-07-23 20:27:58 -07:00
Henry Cook
5c00d0a030 new tilelink arbiter type 2013-07-09 15:31:46 -07:00
Andrew Waterman
7cc53c7725 clean up Str 2013-06-15 00:45:53 -07:00
Andrew Waterman
95c5147dc5 Add RISC-V instruction disassembler 2013-06-13 10:31:04 -07:00
Henry Cook
569d8fd796 Merge branch 'tilelink-data' 2013-05-23 14:14:40 -07:00
Henry Cook
12205b9684 remove obsolete config file reader prototype 2013-05-23 14:09:03 -07:00
Andrew Waterman
fe9adfe71b Simplify and correct integer multiplier 2013-05-22 17:27:50 -07:00
Yunsup Lee
11133d6d4c clock gate s2 registers in the frontend 2013-05-21 18:59:21 -07:00
Yunsup Lee
c837c1d800 fix bug in previous JALR commit 
on commit tag 9a122c06d1bf11237d7fb0769d454a67bbb7400e
 2013-05-21 18:28:44 -07:00
Henry Cook
69b508ff39 ported caches and htif to use new tilelink 2013-05-21 17:21:04 -07:00
Andrew Waterman
28f914c3f2 don't JALR to speculatively-bypassed addresses 
Technically not necessary, but probably improves performance.
 2013-05-21 16:56:58 -07:00
Yunsup Lee
dcde377303 Fix DM I$ deadlock 
BTB predictions were causing infinite miss loops
 2013-05-20 15:22:58 -07:00
Andrew Waterman
3a1b5f01b2 don't take interrupts while they're disabled! 
a control bug allowed an interrupt to be taken on the instruction immediately
following an interrupt-disabling instruction (but not thereafter).
 2013-05-19 23:27:47 -07:00
Andrew Waterman
6eb4c2542a comment out I$ assert for now 2013-05-18 18:09:23 -07:00
Andrew Waterman
1dab984231 use UFix instead of Bits for arithmetic 2013-05-18 00:45:29 -07:00
Andrew Waterman
dfa7a03f73 use assert, not Assert 2013-05-18 00:45:13 -07:00
Andrew Waterman
d405ffa949 assume all I$ grants bear data 2013-05-01 21:01:20 -07:00
Andrew Waterman
474d321cc7 fix meta hazard counter to reset on new meta writes 2013-05-01 16:35:24 -07:00
Andrew Waterman
a6a88fce19 Revert "broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle" 
This reverts commit b41e6bc50519631ba097ac1196737be7107295f9.
 2013-05-01 16:34:45 -07:00
Andrew Waterman
63a38e7982 Revert "temp" 
This reverts commit 73705e6ed8f98d08ce6b30fbe760de694c6563ae.
 2013-05-01 16:34:33 -07:00
Henry Cook
b6945408cb temp 2013-05-01 10:24:36 -07:00
Henry Cook
722bc917d3 broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle 2013-05-01 10:05:54 -07:00
Andrew Waterman
1501e90c1f interlock probe unit on tag RAW hazards 2013-04-30 00:38:22 -07:00
Henry Cook
e8b20f3d38 clear meta state of silently-dropped, clean evictee, so as to prevent a write race on meta array between probes on evictee and refill grant 2013-04-25 17:41:04 -07:00
Andrew Waterman
50ccc20bf3 replace RDNPC with AUIPC 2013-04-22 04:20:15 -07:00