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Commit Graph

690 Commits

Author SHA1 Message Date
Andrew Waterman
1f986d1c96 Branches don't care about the ALU input/function 2014-01-24 16:37:40 -08:00
Andrew Waterman
a1b7774f5d Simplify handling of CAUSE register 2014-01-24 16:37:39 -08:00
Christopher Celio
a2be21361e Allow ICacheConfig to toggle fetch-width. 2014-01-22 16:19:57 -08:00
Andrew Waterman
a7489920ce Support CSR atomics on all CSRs, not just STATUS 2014-01-21 16:17:39 -08:00
Andrew Waterman
6ba2c1abe5 Use auto-generated CAUSE constants 2014-01-21 15:01:54 -08:00
Andrew Waterman
95de358a96 More of the same FPU fix
some SP ops followed by DP stores were not working because they
were encoded as subnormals, not NaNs.
2014-01-17 14:09:30 -08:00
Andrew Waterman
cf38001e98 Fix fmv.s.x -> fsd 2014-01-17 03:52:35 -08:00
Andrew Waterman
57f4d89c90 Generate D$ replay_next signals correctly 2014-01-16 00:16:09 -08:00
Andrew Waterman
6ebdc4d94e Simplify store conditional failure code generation 2014-01-16 00:15:48 -08:00
Andrew Waterman
31060ea8ae Fix fubar long-latency writeback control logic
Load miss writebacks happening at the same time as multiplication
wasn't working.  Hopefully this does it.
2014-01-14 04:02:43 -08:00
Andrew Waterman
e8486817e6 Clean up formatting (i.e. remove tabs, semicolons) 2014-01-13 21:43:56 -08:00
Andrew Waterman
a50a1f7d50 Clean up multiplier/divider stuff 2014-01-13 21:37:16 -08:00
Andrew Waterman
4d236979bd Fix very far forward JALs
We were sign-extending from the wrong bit, causing a backwards jump.
2014-01-13 00:55:48 -08:00
Andrew Waterman
c546f66404 Swap JAL/JALR encodings (again) 2014-01-13 00:54:49 -08:00
Andrew Waterman
07a91bb99a Miscellaneous cleanup 2013-12-09 19:53:14 -08:00
Andrew Waterman
da3135ac9b Begin integer unit clean-up
...to make it easier to generate the superscalar version of the core.
2013-12-09 15:06:13 -08:00
Andrew Waterman
16d5250924 Correct FP trap behavior on FCSR 2013-12-05 04:18:04 -08:00
Andrew Waterman
5814a90472 Make DecodeLogic interface more flexible 2013-12-05 04:16:48 -08:00
Andrew Waterman
924261e2b2 Update to new privileged ISA... phew 2013-11-25 04:35:15 -08:00
Andrew Waterman
65b8340cea Mitigate D$ hit -> branch -> NPC critical path 2013-11-24 14:21:03 -08:00
Andrew Waterman
53f726008b Use Mem instead of Vec[Reg] for TLB
QoR-neutral, improves simulation speed
2013-11-24 14:21:02 -08:00
Yunsup Lee
68e270eeb2 fix slli/slliw encoding bug 2013-11-21 14:44:58 -08:00
Yunsup Lee
c1966e2b0a forgot to put htif into uncore package 2013-11-07 15:42:03 -08:00
Yunsup Lee
da033af0b0 move htif to uncore 2013-11-07 13:18:46 -08:00
Andrew Waterman
12f0369e6e Simplify divide early out circuitry 2013-10-29 13:20:40 -07:00
Andrew Waterman
b44dafbdca Simplify branch offset mux 2013-10-29 13:20:40 -07:00
Andrew Waterman
23f7bab4f3 Reduce FMA pipeline depths
FMA QoR has improved enough to allow this change.
2013-10-29 13:20:40 -07:00
Yunsup Lee
1583560757 fix replay bug, don't respond when cmd is a NOP 2013-10-28 22:35:18 -07:00
Stephen Twigg
36b85b8ee2 Fix issue where the MSB of D$ req tag was getting lost for all agents when an accelerator was attached. 2013-09-25 11:51:10 -07:00
Stephen Twigg
891e459625 Export stats pcr register (#28 currently) to the top-level 2013-09-25 01:16:32 -07:00
Stephen Twigg
730a6ec76b AccumulatorExample now properly sets its busy bit. Also, pepper some helpful comments into AccumulatorExample 2013-09-24 16:32:49 -07:00
Andrew Waterman
81c752de84 Support disabling virtual memory 2013-09-24 13:58:47 -07:00
Andrew Waterman
adc386f889 Turn off virtual memory inside RoCC base class 2013-09-24 13:58:47 -07:00
Stephen Twigg
3532ae0b79 From Andrew, actually mark scoreboard when rocc instruction with a writeback is issued. Also, fix an issue with AccumulatorExample not properly tagging its memory requests. Finally, reverted changes from f27429c to more properly follow the spike model (always return previous value of accumulator). 2013-09-24 10:54:09 -07:00
Stephen Twigg
db1e09f0d0 Fix issues with RoCC AccumulatorExample stalls on memory interface 2013-09-23 00:21:43 -07:00
Stephen Twigg
158cee08af Adjust ordering of RoCCInstruction to reflect new ISA encoding. (Note: Fixes register op issues with AccumulatorExample but still slight issue with executing memory loads) 2013-09-22 03:18:06 -07:00
Andrew Waterman
1d2f4f8437 New ISA encoding, AUIPC semantics 2013-09-21 06:32:40 -07:00
Andrew Waterman
25ab402932 swap JAL, JALR encodings 2013-09-15 04:29:06 -07:00
Andrew Waterman
110e53cb48 Revert "Add early out to multiplier"
This broke recently and I don't have time to figure out why.
2013-09-15 04:15:32 -07:00
Andrew Waterman
88d1c47665 don't disassemble within chisel 2013-09-15 04:14:45 -07:00
Andrew Waterman
f12bbc1e43 working RoCC AccumulatorExample 2013-09-14 22:34:53 -07:00
Andrew Waterman
18968dfbc7 Move store data generation into cache 2013-09-14 16:15:07 -07:00
Andrew Waterman
a0cb711451 Start adding RoCC 2013-09-14 15:31:50 -07:00
Andrew Waterman
d053bdc89f Remove Hwacha from Rocket
Soon it will use the coprocessor interface.
2013-09-12 22:34:38 -07:00
Andrew Waterman
1edb1e2a0a Ignore LSB of PC 2013-09-12 17:55:58 -07:00
Andrew Waterman
59f5358435 Implement AQ/RL; move fence logic out of cache 2013-09-12 16:07:30 -07:00
Andrew Waterman
243c4ae342 sync up rocket with new isa 2013-09-12 03:44:38 -07:00
Andrew Waterman
95dd0d8be1 Remove DebugIO/error mode 2013-09-11 20:15:21 -07:00
Henry Cook
f9b85d8158 NetworkIOs no longer use thunks 2013-09-10 16:15:19 -07:00
Henry Cook
d06e24ac24 new enum syntax 2013-09-10 10:51:35 -07:00