riscv/rocket-chip
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Author SHA1 Message Date
Howard Mao cd96a66ba6 replace verilog clock divider with one written in Chisel 2016-09-22 11:32:29 -07:00
Howard Mao cbd702e48e make sure junctions and uncore unittests both run 2016-09-21 20:17:52 -07:00
Howard MaoandGitHub 74fc7c5803 Merge pull request #315 from ucb-bar/fix-addrmap-error-msg 
correctly print out the addrmap overlapping error message
 2016-09-19 19:39:56 -07:00
Howard Mao 49863944c4 merge ClientTileLinkEnqueuer and ClientUncachedTileLinkEnqueuer objects into TileLinkEnqueuer 2016-09-14 21:36:27 -07:00
Howard Mao f363f5f709 wrap TestHarness latency pipe in module 2016-09-14 21:16:54 -07:00
Howard Mao f5db83a72f NTiles should not be a Knob 2016-09-14 21:16:54 -07:00
Howard Mao 646527c88e use named constants to set AXI resp, cache, and prot fields 2016-09-14 21:16:54 -07:00
Howard Mao f95b8c4ec2 move UnitTest back into rocketchip module 2016-09-14 20:51:56 -07:00
Howard Mao bf253aaa97 allow MODEL to be something other than TestHarness 2016-09-14 20:51:56 -07:00
Howard Mao 8550582f84 remove redundant verilator rule 2016-09-14 20:31:17 -07:00
Howard Mao bdb7b1de36 move tilelink-agnostic counters from uncore to util package 2016-09-13 20:47:05 -07:00
Howard Mao 1882241493 move junctions utils into top-level utils package 2016-09-13 20:47:04 -07:00
Howard Mao f3cdeb08c6 pass nMemChannels to coreplex through CoreplexConfig 2016-09-12 12:40:10 -07:00
Howard Mao 9d9f90646d allow configuration of simulation memory latency 2016-09-12 12:33:50 -07:00
Howard MaoandGitHub 62e33527d3 Merge branch 'master' into fix-non-contiguous-mmio-region-routing 2016-09-07 23:35:12 -07:00
Howard MaoandGitHub 4592558047 Merge pull request #254 from ucb-bar/inferRW 
Turn on the inferRW Firrtl pass
 2016-09-07 21:59:05 -07:00
Howard MaoandGitHub 7a6f155b2a Merge pull request #253 from ucb-bar/use-companion 
only use companion objects for types
 2016-09-07 15:07:17 -07:00
Howard MaoandGitHub 7504498dff Merge pull request #247 from ucb-bar/replseqmem_pr 
Bump FIRRTL for Sequential Memories
 2016-09-06 17:22:18 -07:00
Howard MaoandGitHub bbef3a8d3e Merge pull request #246 from ucb-bar/fix-configstring-printout-problem 
fix configstring printout with no memory
 2016-09-06 15:31:39 -07:00
Howard MaoandGitHub 59a2e6a4dc Merge pull request #244 from ucb-bar/compelete-dramsim-removal 
remove remaining dramsim2 files
 2016-09-05 15:05:38 -07:00
Howard Mao 8906097250 have Travis cache the entire verilator directory 2016-09-04 15:05:30 -07:00
Howard Mao a7f79aa409 get rid of TileLinkMemorySelector 2016-09-04 10:55:19 -07:00
Howard Mao f0ab6d0214 tie off finish signals in tilelink wrapper and unwrapper 2016-09-04 10:55:19 -07:00
Howard Mao 66de89c4db allow fixed priority routing in Junctions arbiters 2016-09-04 10:55:19 -07:00
Howard Mao efe8670283 allow Serializer/Deserializer to work with arbitrary Chisel data types 2016-09-04 10:55:19 -07:00
Howard Mao b9b79e4fb6 get rid of AtoS RTL 2016-09-04 10:55:19 -07:00
Howard Mao f34843f1b9 fix assignment of incoherent vector 2016-09-04 10:12:16 -07:00
Howard Mao 08089f695d allow configuration to be in separate project from test harness 2016-09-01 10:28:07 -07:00
Howard Mao c66318307c no longer need to set invalidate_lr in RoCC examples 2016-08-31 22:05:35 -07:00
Howard Mao 27c674972c tie off invalidate_lr in RoCC 2016-08-31 22:00:27 -07:00
Howard Mao bb578494d8 don't override req.bits.phys in SimpleHellaCacheIF 2016-08-31 22:00:27 -07:00
Howard Mao 50d6738caf make sure DummyPTW sets all the necessary status and ptbr signals 2016-08-31 22:00:27 -07:00
Howard Mao 403cc1c5c4 fix DecoupledTLB to handle misses appropriately 2016-08-31 22:00:27 -07:00
Howard MaoandGitHub cf1bd90a70 Merge pull request #234 from zizztux/fix_export_mmio 
Add address map entries for exported mmio port.
 2016-08-30 15:58:01 -07:00
Howard MaoandAndrew Waterman a19bd6de96 Get in line with FIRRTL randomization flag changes (#231) 2016-08-29 12:29:01 -07:00
Howard Mao 61aa716f44 fix bus axi connections in periphery 2016-08-22 11:57:15 -07:00
Howard Mao f9ea14b4c2 extra devices should get elaborated in a single build function 2016-08-22 11:57:15 -07:00
Howard Mao ceff6dd0c8 update README 2016-08-19 13:45:23 -07:00
Howard Mao 40bd87bce4 cache the verilator install in travis 2016-08-19 13:45:23 -07:00
Howard Mao 1c5034707b fix submodules in regression makefile 2016-08-19 13:45:23 -07:00
Howard Mao f4e0e0966c move rocketchip package sources into its own subdirectory 2016-08-19 13:45:23 -07:00
Howard Mao eba692786b make sure FIRRTL jar gets updated timestamp 2016-08-19 13:45:23 -07:00
Howard Mao 7b20609d4d reorganize moving non-submodule packages into src/main/scala 2016-08-19 13:45:23 -07:00
Howard Mao f78da0b0ea add required cloneType methods in non-blocking L1 2016-08-19 13:44:53 -07:00
Howard Mao 33676e81f8 use isOneOf as much as possible 2016-08-19 09:56:06 -07:00
Howard Mao d34e790ac0 get rid of duplicated code in rocket Util 2016-08-18 18:40:07 -07:00
Howard Mao 7671811ac9 merge uncore.Util into uncore.util 2016-08-18 18:33:46 -07:00
Howard Mao 91a97d6773 add some more comments to describe the new device system 2016-08-18 15:06:55 -07:00
Howard Mao 1b6fa70b5c Add test for external TL clients (bus mastering) 2016-08-18 14:26:03 -07:00
Howard Mao 18982d7351 add default addrMapEntry definition which throws exception 2016-08-18 12:29:41 -07:00
Howard Mao f7c42499bb allow ExtraDevices to have client ports as well as MMIO ports 2016-08-18 12:18:14 -07:00
Howard Mao d771f37e7e rename BusPorts to ExternalClients 2016-08-18 10:54:24 -07:00
Howard Mao 10190197c3 allow coreplex to take in more than 1 bus port 2016-08-18 10:35:25 -07:00
Howard Mao 35fbbfc70d put test harness on the heap in emulator 2016-08-16 14:50:40 -07:00
Howard MaoandAndrew Waterman 38e0967816 strip DMA and RoCC CSRs out of rocket and uncore (#201) 2016-08-15 23:08:55 -07:00
Howard Mao 47a0c880a4 make sure TLId set in Periphery 2016-08-15 13:58:23 -07:00
Howard Mao e939af88aa explicitly set TLId for bus TL ports 2016-08-15 12:46:29 -07:00
Howard Mao 2c39f039b5 make external address map order overrideable 2016-08-15 11:40:28 -07:00
Howard Mao fb476d193c refactor main App for better code re-use 2016-08-11 16:15:23 -07:00
Howard Mao a756856d84 make sure coreplex sources included in make dependencies 2016-08-11 14:27:03 -07:00
Howard Mao e0ae039235 fix config string generation for extra devices 2016-08-11 10:44:32 -07:00
Howard Mao 647dbefd9b split coreplex off into separate package 2016-08-10 18:04:22 -07:00
Howard Mao 163cba6a85 make sure all regressions actually run 2016-08-10 14:52:06 -07:00
Howard Mao 4bfa7ceb6a unit tests in Coreplex instead of Tile 2016-08-10 11:26:14 -07:00
Howard Mao 571d579b86 get unit tests working again 2016-08-10 11:23:07 -07:00
Howard Mao 0ee1ce4366 separate Coreplex and TopLevel parameter traits 2016-08-10 09:49:56 -07:00
Howard Mao f95d319162 don't use secondary external address map; collapse submap instead 2016-08-09 22:29:38 -07:00
Howard Mao 2645f74af2 clean up addrmap flatten function 2016-08-09 22:14:32 -07:00
Howard Mao 33f13d5c49 don't repeat external addr map base 2016-08-09 21:20:54 -07:00
Howard Mao 3ea2f4a6c4 refactor top-level into coreplex and platform 2016-08-09 18:26:52 -07:00
Howard Mao 993da60f2c relax address map alignment requirement 2016-08-09 18:25:32 -07:00
Howard Mao 33d5905c50 don't synthesize vsim verilog in Travis 2016-08-09 18:24:59 -07:00
Howard Mao 405294167f fix TL -> Nasti converter w id 2016-08-09 18:24:23 -07:00
Howard MaoandAndrew Waterman 2a5aeeae24 add sbt pack plugin (#197) 2016-08-08 19:31:03 -07:00
Howard Mao dd1fed41b6 generate BootROM contents from assembly code 2016-08-05 16:39:21 -07:00
Howard Mao 9fa5b228b2 allow extra devices and top-level ports to be added without changing RocketChip.scala 2016-08-04 14:06:14 -07:00
Howard Mao 9c4e57aea5 example Rocc accelerator fixes 2016-08-04 11:17:13 -07:00
Howard Mao 410e3e5366 make sure TraceGen gets correct addresses 2016-08-04 11:08:25 -07:00
Howard Mao 0a85e92652 Allow additional internal MMIO devices to be created without changing BaseConfig 2016-08-04 11:04:52 -07:00
Howard Mao f04aefc95c get rid of deprecated ZynqAdapter 2016-08-02 13:14:20 -07:00
Howard Mao 63b814fcd7 only run the important (high coverage) tests in regression suite 2016-08-02 10:54:05 -07:00
Howard Mao b7723f1ff8 make unit tests local to the packages being tested 2016-08-01 17:02:00 -07:00
Howard Mao 98eede0505 some refactoring in RocketChip top-level 2016-08-01 17:02:00 -07:00
Howard Mao f34b0b0447 make sure L2 tracker doesn't read data array again if data buffer already filled 2016-07-29 16:47:31 -07:00
Howard Mao 2891eb879a add MergedPutRegression to uncover merged put after release bug in L2 2016-07-29 16:42:28 -07:00
Howard Mao 064020bdd7 make sure Memtest generators write different data to each address 2016-07-29 14:22:46 -07:00
Howard Mao 5a3beca097 add RepeatedGetRegression to uncover L2 merged get miss bug 2016-07-28 19:58:47 -07:00
Howard Mao cb86aaa46b fix trace generator addresses 2016-07-28 17:56:14 -07:00
Howard Mao bd5972503f move groundtest/scripts to top-level scripts/ 2016-07-28 11:36:55 -07:00
Howard Mao 478f494626 Merge remote-tracking branch 'groundtest/master' into mono-repo 2016-07-28 11:28:06 -07:00
Howard Mao a5b88d0bdc Merge remote-tracking branch 'junctions/master' into mono-repo 2016-07-28 11:27:47 -07:00
Howard Mao 373fd427dc Merge remote-tracking branch 'rocket/master' into mono-repo 2016-07-28 11:27:29 -07:00
Howard Mao ce242b8f3f Merge remote-tracking branch 'uncore/master' into mono-repo 2016-07-28 11:23:31 -07:00
Howard Mao aefba04fb3 get rid of submodules in preparation for merging 2016-07-28 11:21:08 -07:00
Howard Mao 6de2a3e3b1 get rid of fpga-zynq submodule 2016-07-28 11:07:47 -07:00
Howard Mao fe51a35fa9 a few more submodule bumps 2016-07-28 09:25:59 -07:00
Howard Mao bf35f980a6 make sure PTE cache is power of 2 in size to satisfy PseudoLRU requirement 2016-07-27 18:40:38 -07:00
Howard Mao fbcc7317cf make sure PseudoLRU is given power of 2 ways 2016-07-27 18:39:33 -07:00
Howard Mao 15d1aa9346 make sure TrackerAllocationIO addr_block has correct direction set 2016-07-27 16:47:22 -07:00
Howard Mao 9c89290efc fix LRSC issue (fixes issue #86) 2016-07-26 22:25:04 -07:00