Merge pull request #247 from ucb-bar/replseqmem_pr
Bump FIRRTL for Sequential Memories
This commit is contained in:
Howard Mao
GitHub
commit
7504498dff
2
firrtl
2
firrtl
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@ -1 +1 @@
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Subproject commit a2af16c1fb1f5166eab34188df9944012da3cbc3
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Subproject commit 6a05468ed0ece1ace3019666b16f2ae83ef76ef9
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@ -11,7 +11,8 @@ default: all
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base_dir = $(abspath ..)
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generated_dir = $(abspath ./generated-src)
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mem_gen = $(base_dir)/vsim/vlsi_mem_gen
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VLSI_MEM_GEN ?= $(base_dir)/vsim/vlsi_mem_gen
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mem_gen = $(VLSI_MEM_GEN)
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sim_dir = .
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output_dir = $(sim_dir)/output
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@ -10,6 +10,7 @@ bb_vsrcs = $(base_dir)/vsrc/DebugTransportModuleJtag.v \
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sim_vsrcs = \
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$(generated_dir)/$(MODEL).$(CONFIG).v \
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$(generated_dir)/$(MODEL).$(CONFIG).behav_srams.v \
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$(generated_dir)/consts.$(CONFIG).vh \
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$(base_dir)/vsrc/$(TB).v \
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$(base_dir)/vsrc/SimDTM.v \
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@ -9,9 +9,15 @@ $(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)
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mkdir -p $(dir $@)
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cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(notdir $*) $(CFG_PROJECT) $(CONFIG)"
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$(generated_dir)/%.v: $(generated_dir)/%.fir $(FIRRTL_JAR)
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$(generated_dir)/%.v $(generated_dir)/%.conf : $(generated_dir)/%.fir $(FIRRTL_JAR)
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mkdir -p $(dir $@)
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$(FIRRTL) -i $< -o $@ -X verilog
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$(FIRRTL) -i $< -o $@ -X verilog --replSeqMem -c:$(MODEL):-o:$(generated_dir)/$(MODEL).$(CONFIG).conf
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$(generated_dir)/$(MODEL).$(CONFIG).behav_srams.v : $(generated_dir)/$(MODEL).$(CONFIG).conf $(mem_gen)
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cd $(generated_dir) && \
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rm -f $@ && \
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$(mem_gen) $(generated_dir)/$(MODEL).$(CONFIG).conf >> $@.tmp && \
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mv $@.tmp $@
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$(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).prm
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echo "\`ifndef CONST_VH" > $@
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@ -12,7 +12,7 @@ def parse_line(line):
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width = 0
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depth = 0
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ports = ''
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mask_gran = 1
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mask_gran = 0
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tokens = line.split()
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i = 0
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for i in range(0,len(tokens),2):
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@ -21,20 +21,20 @@ def parse_line(line):
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name = tokens[i+1]
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elif s == 'width':
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width = int(tokens[i+1])
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mask_gran = width # default setting
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elif s == 'depth':
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depth = int(tokens[i+1])
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elif s == 'ports':
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ports = tokens[i+1].split(',')
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elif s == 'mask_gran':
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# currently used only for fpga, but here for .conf format compatability
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mask_gran = int(tokens[i+1])
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else:
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sys.exit('%s: unknown argument %s' % (sys.argv[0], a))
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return (name, width, depth, ports)
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return (name, width, depth, mask_gran, width/mask_gran, ports)
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def gen_mem(name, width, depth, ports):
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def gen_mem(name, width, depth, mask_gran, mask_seg, ports):
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addr_width = max(math.ceil(math.log(depth)/math.log(2)),1)
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port_spec = ['input CLK', 'input RST', 'input init']
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port_spec = []
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readports = []
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writeports = []
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latchports = []
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@ -50,28 +50,34 @@ def gen_mem(name, width, depth, ports):
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maskedports[pid] = pid
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if ptype == 'read':
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port_spec.append('input [%d:0] R%dA' % (addr_width-1, pid))
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port_spec.append('input R%dE' % pid)
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port_spec.append('output [%d:0] R%dO' % (width-1, pid))
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prefix = 'R%d_' % len(readports)
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port_spec.append('input %sclk' % prefix)
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port_spec.append('input [%d:0] %saddr' % (addr_width-1, prefix))
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port_spec.append('input %sen' % prefix)
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port_spec.append('output [%d:0] %sdata' % (width-1, prefix))
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readports.append(pid)
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elif ptype == 'write':
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port_spec.append('input [%d:0] W%dA' % (addr_width-1, pid))
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port_spec.append('input W%dE' % pid)
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port_spec.append('input [%d:0] W%dI' % (width-1, pid))
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prefix = 'W%d_' % len(writeports)
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port_spec.append('input %sclk' % prefix)
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port_spec.append('input [%d:0] %saddr' % (addr_width-1, prefix))
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port_spec.append('input %sen' % prefix)
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port_spec.append('input [%d:0] %sdata' % (width-1, prefix))
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if pid in maskedports:
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port_spec.append('input [%d:0] W%dM' % (width-1, pid))
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port_spec.append('input [%d:0] %smask' % (mask_seg-1, prefix))
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if not use_latches or pid in maskedports:
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writeports.append(pid)
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else:
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latchports.append(pid)
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elif ptype == 'rw':
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port_spec.append('input [%d:0] RW%dA' % (addr_width-1, pid))
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port_spec.append('input RW%dE' % pid)
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port_spec.append('input RW%dW' % pid)
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prefix = 'RW%d_' % len(rwports)
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port_spec.append('input %sclk' % prefix)
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port_spec.append('input [%d:0] %saddr' % (addr_width-1, prefix))
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port_spec.append('input %sen' % prefix)
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port_spec.append('input %swmode' % prefix)
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if pid in maskedports:
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port_spec.append('input [%d:0] RW%dM' % (width-1, pid))
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port_spec.append('input [%d:0] RW%dI' % (width-1, pid))
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port_spec.append('output [%d:0] RW%dO' % (width-1, pid))
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port_spec.append('input [%d:0] %swmask' % (mask_seg-1, prefix))
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port_spec.append('input [%d:0] %swdata' % (width-1, prefix))
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port_spec.append('output [%d:0] %srdata' % (width-1, prefix))
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rwports.append(pid)
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else:
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sys.exit('%s: unknown port type %s' % (sys.argv[0], ptype))
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@ -82,66 +88,83 @@ def gen_mem(name, width, depth, ports):
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masked = len(maskedports)>0
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tup = (depth, width, nr, nw, nrw, masked)
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for pid in readports:
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decl.append('reg [%d:0] reg_R%dA;' % (addr_width-1, pid))
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sequential.append('if (R%dE) reg_R%dA <= R%dA;' % (pid, pid, pid))
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combinational.append('assign R%dO = ram[reg_R%dA];' % (pid, pid))
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for idx in range(nr):
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prefix = 'R%d_' % idx
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decl.append('reg [%d:0] reg_%saddr;' % (addr_width-1, prefix))
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sequential.append('always @(posedge %sclk)' % prefix)
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sequential.append(' if (%sen) reg_%saddr <= %saddr;' % (prefix, prefix, prefix))
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combinational.append('assign %sdata = ram[reg_%saddr];' % (prefix, prefix))
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for pid in rwports:
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decl.append('reg [%d:0] reg_RW%dA;' % (addr_width-1, pid))
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sequential.append('if (RW%dE && !RW%dW) reg_RW%dA <= RW%dA;' % (pid, pid, pid, pid))
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combinational.append('assign RW%dO = ram[reg_RW%dA];' % (pid, pid))
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for idx in range(nrw):
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prefix = 'RW%d_' % idx
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decl.append('reg [%d:0] reg_%saddr;' % (addr_width-1, prefix))
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sequential.append('always @(posedge %sclk)' % prefix)
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sequential.append(' if (%sen && !%swmode) reg_%saddr <= %saddr;' % (prefix, prefix, prefix, prefix))
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combinational.append('assign %srdata = ram[reg_%saddr];' % (prefix, prefix))
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for pid in latchports:
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decl.append('reg [%d:0] latch_W%dA;' % (addr_width-1, pid))
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decl.append('reg [%d:0] latch_W%dI;' % (width-1, pid))
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decl.append('reg latch_W%dE;' % (pid))
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for idx in range(len(latchports)):
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prefix = 'W%d_' % idx
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decl.append('reg [%d:0] latch_%saddr;' % (addr_width-1, prefix))
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decl.append('reg [%d:0] latch_%sdata;' % (width-1, prefix))
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decl.append('reg latch_%sen;' % (prefix))
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combinational.append('always @(*) begin')
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combinational.append(' if (!CLK && W%dE) latch_W%dA <= W%dA;' % (pid, pid, pid))
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combinational.append(' if (!CLK && W%dE) latch_W%dI <= W%dI;' % (pid, pid, pid))
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combinational.append(' if (!CLK) latch_W%dE <= W%dE;' % (pid, pid))
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combinational.append(' if (!%sclk && %sen) latch_%saddr <= %saddr;' % (prefix, prefix, prefix, prefix))
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combinational.append(' if (!%sclk && %sen) latch_%sdata <= %sdata;' % (prefix, prefix, prefix, prefix))
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combinational.append(' if (!%sclk) latch_%sen <= %sen;' % (prefix, prefix, prefix))
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combinational.append('end')
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combinational.append('always @(*)')
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combinational.append(' if (CLK && latch_W%dE)' % (pid))
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combinational.append(' ram[latch_W%dA] <= latch_W%dI;' % (pid, pid))
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combinational.append(' if (%sclk && latch_%sen)' % (prefix, prefix))
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combinational.append(' ram[latch_%saddr] <= latch_%sdata;' % (prefix, prefix))
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decl.append('reg [%d:0] ram [%d:0];' % (width-1, depth-1))
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decl.append('`ifndef SYNTHESIS')
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decl.append('`ifdef RANDOMIZE')
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decl.append(' integer initvar;')
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decl.append(' initial begin')
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decl.append(' #0.002;')
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decl.append(' for (initvar = 0; initvar < %d; initvar = initvar+1)' % depth)
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decl.append(' ram[initvar] = {%d {$random}};' % ((width-1)/32+1))
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for pid in readports:
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decl.append(' reg_R%dA = {%d {$random}};' % (pid, ((addr_width-1)/32+1)))
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for pid in rwports:
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decl.append(' reg_RW%dA = {%d {$random}};' % (pid, ((addr_width-1)/32+1)))
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for idx in range(nr):
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prefix = 'R%d_' % idx
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decl.append(' reg_%saddr = {%d {$random}};' % (prefix, ((addr_width-1)/32+1)))
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for idx in range(nrw):
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prefix = 'RW%d_' % idx
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decl.append(' reg_%saddr = {%d {$random}};' % (prefix, ((addr_width-1)/32+1)))
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decl.append(' end')
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decl.append('`endif')
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decl.append("integer i;")
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sequential.append("for (i = 0; i < %d; i=i+1) begin" % width)
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for pid in writeports:
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mask = (' && W%dM[i]' % pid) if pid in maskedports else ''
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sequential.append(" if (W%dE%s) ram[W%dA][i] <= W%dI[i];" % (pid, mask, pid, pid))
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for pid in rwports:
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mask = (' && RW%dM[i]' % pid) if pid in maskedports else ''
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sequential.append(" if (RW%dE && RW%dW%s) ram[RW%dA][i] <= RW%dI[i];" % (pid, pid, mask, pid, pid))
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sequential.append("end")
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for idx in range(nw):
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prefix = 'W%d_' % idx
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pid = writeports[idx]
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sequential.append('always @(posedge %sclk)' % prefix)
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sequential.append(" if (%sen) begin" % prefix)
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for i in range(mask_seg):
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mask = ('if (%smask[%d]) ' % (prefix, i)) if pid in maskedports else ''
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ram_range = '%d:%d' % ((i+1)*mask_gran-1, i*mask_gran)
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sequential.append(" %sram[%saddr][%s] <= %sdata[%s];" % (mask, prefix, ram_range, prefix, ram_range))
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sequential.append(" end")
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for idx in range(nrw):
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pid = rwports[idx]
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prefix = 'RW%d_' % idx
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sequential.append('always @(posedge %sclk)' % prefix)
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sequential.append(" if (%sen && %swmode) begin" % (prefix, prefix))
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for i in range(mask_seg):
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mask = ('if (%swmask[%d]) ' % (prefix, i)) if pid in maskedports else ''
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ram_range = '%d:%d' % ((i+1)*mask_gran-1, i*mask_gran)
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sequential.append(" %sram[%saddr][%s] <= %swdata[%s];" % (mask, prefix, ram_range, prefix, ram_range))
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sequential.append(" end")
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body = "\
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%s\n\
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always @(posedge CLK) begin\n\
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%s\n\
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end\n\
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%s\n" % ('\n '.join(decl), '\n '.join(sequential), '\n '.join(combinational))
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%s\n\
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%s\n" % ('\n '.join(decl), '\n '.join(sequential), '\n '.join(combinational))
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s = "module %s(\n\
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s = "\nmodule %s(\n\
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%s\n\
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);\n\
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\n\
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%s\
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\n\
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endmodule\n" % (name, ',\n '.join(port_spec), body)
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endmodule" % (name, ',\n '.join(port_spec), body)
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return s
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def main():
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