riscv/rocket-chip
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NTiles should not be a Knob

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This commit is contained in:
Howard Mao 2016-09-13 11:29:26 -07:00
parent 646527c88e
commit f5db83a72f
1 changed files with 4 additions and 3 deletions
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7
src/main/scala/coreplex/Configs.scala
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@ -189,7 +189,7 @@ class BaseCoreplexConfig extends Config (
case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
case BootROMFile => "./bootrom/bootrom.img"
case NTiles => Knob("NTILES")
case NTiles => 1
case NBanksPerMemoryChannel => Knob("NBANKS_PER_MEM_CHANNEL")
case BankIdLSB => 0
case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64)
@ -224,7 +224,6 @@ class BaseCoreplexConfig extends Config (
case _ => throw new CDEMatchError
}},
knobValues = {
case "NTILES" => 1
case "NBANKS_PER_MEM_CHANNEL" => 1
case "L1D_MSHRS" => 2
case "L1D_SETS" => 64
@ -236,7 +235,9 @@ class BaseCoreplexConfig extends Config (
)
class WithNCores(n: Int) extends Config(
knobValues = { case"NTILES" => n; case _ => throw new CDEMatchError })
(pname,site,here) => pname match {
case NTiles => n
})
class WithNBanksPerMemChannel(n: Int) extends Config(
knobValues = {