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7bb7299018
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Don't pollute BTB with PC+4 target predictions
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2014-10-14 17:28:37 -07:00 |
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8abf62fae3
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add LICENSE
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2014-09-12 18:06:41 -07:00 |
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2de268b3b1
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Cache utility traits. Completely compiles, asm tests hang.
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2014-08-19 11:38:20 -07:00 |
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0dac9a7467
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Full conversion to params. Compiles but does not elaborate.
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2014-08-19 11:38:02 -07:00 |
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4e6d69892d
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Added initial brainstorm for parameter hierarchical flattening, does not compile ;)
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2014-08-19 11:37:50 -07:00 |
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812353bace
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Ported FPU parameters to new Chisel Parameters
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2014-08-19 11:37:27 -07:00 |
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3828c628c3
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Remove vestigial control signals
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2014-06-14 13:58:07 -07:00 |
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ac88ded35a
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Use ROMs to reduce node count and improve QoR a bit
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2014-06-14 13:58:07 -07:00 |
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1fa505f9ff
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remove superfluous AVec object
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2014-04-16 17:19:32 -07:00 |
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3520620fbd
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Remove D$ -> BTB path
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2014-04-15 23:05:02 -07:00 |
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de492b3cf7
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Fix critical path through integer scoreboard
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2014-04-15 21:28:13 -07:00 |
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f235fa0db6
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Move branch resolution to M stage
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2014-04-07 15:58:49 -07:00 |
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db59fc65ab
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Add return address stack
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2014-04-01 15:01:27 -07:00 |
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1b030777ce
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Remove vestigial control signal
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2014-03-24 04:36:12 -07:00 |
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943d7ac80a
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Use LinkedHashSet/Map for simpler determinism
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2014-03-15 17:31:48 -07:00 |
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53d62cb69d
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remove nondeterminism
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2014-03-15 16:45:58 -07:00 |
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00bc1a2293
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Add fclass.{s|d} instructions
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2014-03-10 16:59:24 -07:00 |
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c7110c8389
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Make FPU pipeline depths configurable
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2014-02-28 13:39:59 -08:00 |
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a09ff9fdc7
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Revert to old AUIPC definition
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2014-02-10 19:04:42 -08:00 |
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1456170c6d
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Always stall decode on RoCC -> FENCE; never stall on RoCC -> deferred AMO.RL fence
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2014-02-06 12:01:49 -08:00 |
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ff7cae29f7
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hookup rocc interrupt and s bit
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2014-02-06 00:09:42 -08:00 |
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6a02d15c21
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Merge branch 'master' into hwacha-port
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2014-02-04 17:05:03 -08:00 |
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febd26f505
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Correct CSR privilege logic
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2014-01-31 01:03:17 -08:00 |
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3c3c469725
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Add exception signal to rocc interface
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2014-01-28 22:13:16 -08:00 |
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267394d3cc
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Fix CSR interlocks
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2014-01-24 16:37:40 -08:00 |
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1f986d1c96
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Branches don't care about the ALU input/function
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2014-01-24 16:37:40 -08:00 |
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a1b7774f5d
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Simplify handling of CAUSE register
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2014-01-24 16:37:39 -08:00 |
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6ba2c1abe5
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Use auto-generated CAUSE constants
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2014-01-21 15:01:54 -08:00 |
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57f4d89c90
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Generate D$ replay_next signals correctly
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2014-01-16 00:16:09 -08:00 |
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31060ea8ae
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Fix fubar long-latency writeback control logic
Load miss writebacks happening at the same time as multiplication
wasn't working. Hopefully this does it.
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2014-01-14 04:02:43 -08:00 |
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e8486817e6
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Clean up formatting (i.e. remove tabs, semicolons)
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2014-01-13 21:43:56 -08:00 |
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07a91bb99a
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Miscellaneous cleanup
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2013-12-09 19:53:14 -08:00 |
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da3135ac9b
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Begin integer unit clean-up
...to make it easier to generate the superscalar version of the core.
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2013-12-09 15:06:13 -08:00 |
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16d5250924
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Correct FP trap behavior on FCSR
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2013-12-05 04:18:04 -08:00 |
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924261e2b2
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Update to new privileged ISA... phew
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2013-11-25 04:35:15 -08:00 |
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65b8340cea
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Mitigate D$ hit -> branch -> NPC critical path
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2013-11-24 14:21:03 -08:00 |
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3532ae0b79
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From Andrew, actually mark scoreboard when rocc instruction with a writeback is issued. Also, fix an issue with AccumulatorExample not properly tagging its memory requests. Finally, reverted changes from f27429c to more properly follow the spike model (always return previous value of accumulator).
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2013-09-24 10:54:09 -07:00 |
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1d2f4f8437
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New ISA encoding, AUIPC semantics
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2013-09-21 06:32:40 -07:00 |
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f12bbc1e43
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working RoCC AccumulatorExample
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2013-09-14 22:34:53 -07:00 |
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a0cb711451
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Start adding RoCC
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2013-09-14 15:31:50 -07:00 |
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d053bdc89f
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Remove Hwacha from Rocket
Soon it will use the coprocessor interface.
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2013-09-12 22:34:38 -07:00 |
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59f5358435
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Implement AQ/RL; move fence logic out of cache
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2013-09-12 16:07:30 -07:00 |
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243c4ae342
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sync up rocket with new isa
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2013-09-12 03:44:38 -07:00 |
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d1b5076fee
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Don't update BTB when garbage was fetched
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2013-08-24 14:44:11 -07:00 |
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52e31f3298
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Bypass scoreboard updates
This reduces div/mul/D$ miss latency by 1 cycle.
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2013-08-24 14:44:04 -07:00 |
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d4a0db4575
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Reflect ISA changes
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2013-08-24 14:43:55 -07:00 |
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3a266cbbfa
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final Reg changes
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2013-08-15 15:28:15 -07:00 |
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b570435847
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Reg standardization
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2013-08-13 17:50:02 -07:00 |
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1a9e43aa11
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initial attempt at upgrade
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2013-08-12 10:39:11 -07:00 |
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9abdf4e154
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Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
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2013-07-23 20:27:58 -07:00 |
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