Andrew Waterman
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e9eca6a95d
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refactor I$ config; remove Top class
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2012-11-04 16:59:36 -08:00 |
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Andrew Waterman
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4ed2d614a2
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update to new rocket; retime fpu in dc-syn
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2012-11-04 16:43:02 -08:00 |
|
Andrew Waterman
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7380c9fe60
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aggressively clock gate int and fp datapaths
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2012-11-04 16:40:14 -08:00 |
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Andrew Waterman
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bd2d61de03
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use 8T SRAM for I$; gate clock more aggressively
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2012-11-04 16:39:25 -08:00 |
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Andrew Waterman
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fedee6c67d
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add generic error correcting codes
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2012-10-30 01:03:47 -07:00 |
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Henry Cook
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0cd0f8a9db
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Initial version of migratory protocol
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2012-10-23 18:01:53 -07:00 |
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Henry Cook
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538b23c223
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Initial version of using sbt tasks to elaborate chisel source and invoke backends' makefiles
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2012-10-23 12:52:59 -07:00 |
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Henry Cook
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17d2bd8926
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Initial version of sbt tasks (elaborate task with no parameters)
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2012-10-23 12:52:00 -07:00 |
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Yunsup Lee
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3edc1f42aa
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revamp the backup memory link in the vlsi backend
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2012-10-23 03:31:34 -07:00 |
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Andrew Waterman
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367b5489d1
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first crack at continuous compilation/testing flow
try it out: cd emulator; make test
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2012-10-19 04:09:07 -07:00 |
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Andrew Waterman
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1ad928cfe2
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directly integrate dramsim build
also, build it as a static library to simplify dependencies
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2012-10-18 18:59:37 -07:00 |
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Andrew Waterman
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edf0eeed01
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integrate updated rocket/uncore
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2012-10-18 17:51:41 -07:00 |
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Andrew Waterman
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5773cbb68a
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rejigger htif to use UncoreConfiguration
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2012-10-18 17:26:03 -07:00 |
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Andrew Waterman
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2aecb0024f
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UncoreConfiguration now contains coherence policy
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2012-10-18 16:57:28 -07:00 |
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Andrew Waterman
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ffda0e41a9
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parameterize width of MemSerdes/MemDesser
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2012-10-18 16:56:36 -07:00 |
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Henry Cook
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e2eb7ce8e9
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Cleanup git incompetence
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2012-10-16 16:54:58 -07:00 |
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Henry Cook
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88ac5af181
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Merged consts-as-traits
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2012-10-16 16:32:35 -07:00 |
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Henry Cook
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9df5cfa552
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Factored out tilelink classes
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2012-10-16 14:26:33 -07:00 |
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Henry Cook
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6cff1c13d8
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Refer to traits moved to uncore, add UncoreConfiguration to top
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2012-10-16 14:22:23 -07:00 |
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Henry Cook
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8509cda813
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Refined traits for use with rocket asserts, added UncoreConfiguration to handle ntiles
|
2012-10-16 13:58:18 -07:00 |
|
Miquel Moreto
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6d49dc51a0
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Fixed emulator Makefile + extra info in the README file
|
2012-10-16 11:06:48 -07:00 |
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Andrew Waterman
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b9a2af697d
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turn off HAVE_VEC as it's currently broken
the new I$/frontend needs to be integrated
|
2012-10-16 07:38:19 -07:00 |
|
Andrew Waterman
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0a640f2cc6
|
make DecodeLogic deterministic (hopefully)
|
2012-10-16 04:51:21 -07:00 |
|
Andrew Waterman
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5821900329
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don't refetch from I$ if on same 16B block
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2012-10-16 02:24:38 -07:00 |
|
Andrew Waterman
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b955985b38
|
improve divider QoR
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2012-10-16 02:24:38 -07:00 |
|
Andrew Waterman
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197154c485
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use BTB for JALR
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2012-10-16 02:24:37 -07:00 |
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Andrew Waterman
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fc648d13a1
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remove old Mux1H; add implicit conversions
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2012-10-16 02:24:37 -07:00 |
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Andrew Waterman
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661f8e635b
|
merge I$, ITLB, BTB into Frontend
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2012-10-16 02:24:37 -07:00 |
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Andrew Waterman
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fcd69dba98
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add optional early-out to mul/div
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2012-10-16 02:24:37 -07:00 |
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Andrew Waterman
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27ddff1adb
|
simplify and improve multiplier
|
2012-10-16 02:24:37 -07:00 |
|
Henry Cook
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1418604bf0
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new constants organization
|
2012-10-15 18:52:48 -07:00 |
|
Henry Cook
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8970b635b2
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improvements to implicit RocketConfiguration parameter
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2012-10-15 16:29:49 -07:00 |
|
Henry Cook
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a7a4e65690
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Initial verison of reading config from files
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2012-10-15 16:05:50 -07:00 |
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Henry Cook
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5d2a470215
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all rocket-specific arbiters in one file and refactored traits slightly
|
2012-10-15 16:05:32 -07:00 |
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Miquel Moreto
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aa3dc422b4
|
Added first README file
|
2012-10-15 10:54:47 -07:00 |
|
Miquel Moreto
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5d75ddc553
|
Added dramsim2 memory model to the emulator backend
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2012-10-14 14:06:28 -07:00 |
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Yunsup Lee
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34da073077
|
fix tab
|
2012-10-11 12:09:49 -07:00 |
|
Huy Vo
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f67f8829e3
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new rocket + uncore tags, added uncore dependencies to Makefrag
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2012-10-10 15:44:19 -07:00 |
|
Huy Vo
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08ab076217
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forgot to change package + using fromBits in memserdes instead of manual unpacking
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2012-10-10 15:42:39 -07:00 |
|
Huy Vo
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1864e41361
|
memserdes + slowio out of rocket and into uncore
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2012-10-10 15:25:24 -07:00 |
|
Huy Vo
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9610622ab0
|
moving memserdes + slowio into src
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2012-10-10 12:41:11 -07:00 |
|
Huy Vo
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35f213e735
|
Merge branch 'master' of ../rocket-clone
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2012-10-10 12:39:48 -07:00 |
|
Andrew Waterman
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7fd4eb6afd
|
update uncore
|
2012-10-09 18:05:32 -07:00 |
|
Andrew Waterman
|
3973aef938
|
handle structural hazard on LLC tags
|
2012-10-09 18:04:55 -07:00 |
|
Andrew Waterman
|
c3236e6ee6
|
add missing symlink and update uncore
|
2012-10-09 17:51:33 -07:00 |
|
Huy Vo
|
24a49350cc
|
reference chip design
|
2012-10-09 13:05:56 -07:00 |
|
Huy Vo
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fe21142972
|
fixed memdessert unpacking
|
2012-10-09 13:03:17 -07:00 |
|
Huy Vo
|
916c1019af
|
fixed memdessert unpacking
|
2012-10-09 13:03:17 -07:00 |
|
Henry Cook
|
9025d0610c
|
first pass at configuration object passed as implicit parameter
|
2012-10-07 22:37:29 -07:00 |
|
Henry Cook
|
dfdfddebe8
|
constants as traits
|
2012-10-07 22:20:03 -07:00 |
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