Miquel Moreto 5d75ddc553 Added dramsim2 memory model to the emulator backend

2012-10-14 14:06:28 -07:00

chisel @ f07a7ac65c

rename hwacha -> riscv-hwacha, chisel, riscv-asm-tests-bmarks, and uncore tags

2012-10-01 19:12:18 -07:00

csrc

Added dramsim2 memory model to the emulator backend

2012-10-14 14:06:28 -07:00

dramsim2 @ d0045b18ce

Added dramsim2 memory model to the emulator backend

2012-10-14 14:06:28 -07:00

emulator

Added dramsim2 memory model to the emulator backend

2012-10-14 14:06:28 -07:00

hardfloat @ eae838000e

initial commit, all the relevant submodules

2012-09-26 17:46:17 -07:00

project

reference chip design

2012-10-09 13:05:56 -07:00

riscv-rocket @ 2bc0aa2d52

new rocket + uncore tags, added uncore dependencies to Makefrag

2012-10-10 15:44:19 -07:00

src/main/scala

reference chip design

2012-10-09 13:05:56 -07:00

uncore @ 3603d22434

new rocket + uncore tags, added uncore dependencies to Makefrag

2012-10-10 15:44:19 -07:00

.gitmodules

Added dramsim2 memory model to the emulator backend

2012-10-14 14:06:28 -07:00

Makefrag

fix tab

2012-10-11 12:09:49 -07:00

sbt-launch.jar

everything to get emulator working

2012-10-01 19:30:11 -07:00

Description

Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)

13 MiB

Languages

Scala 93.1%

C++ 2.1%

Python 2%

Makefile 1.2%

Verilog 0.8%

Other 0.7%