Andrew Waterman
|
cc7783404d
|
Add memory command M_XA_XOR
|
2013-09-12 16:09:53 -07:00 |
|
Andrew Waterman
|
59f5358435
|
Implement AQ/RL; move fence logic out of cache
|
2013-09-12 16:07:30 -07:00 |
|
Andrew Waterman
|
243c4ae342
|
sync up rocket with new isa
|
2013-09-12 03:44:38 -07:00 |
|
Andrew Waterman
|
95dd0d8be1
|
Remove DebugIO/error mode
|
2013-09-11 20:15:21 -07:00 |
|
Henry Cook
|
b42e140e05
|
NetworkIOs no longer use thunks
|
2013-09-10 16:23:52 -07:00 |
|
Henry Cook
|
1cac26fd76
|
NetworkIOs no longer use thunks
|
2013-09-10 16:15:41 -07:00 |
|
Henry Cook
|
f9b85d8158
|
NetworkIOs no longer use thunks
|
2013-09-10 16:15:19 -07:00 |
|
Henry Cook
|
ee98cd8378
|
new enum syntax
|
2013-09-10 10:54:51 -07:00 |
|
Henry Cook
|
d06e24ac24
|
new enum syntax
|
2013-09-10 10:51:35 -07:00 |
|
Stephen Twigg
|
6cde69e95d
|
Merge changes from master. This updates rocket more than it should so while the emulator builds, programs will not execute correctly due to ISA changes, etc.
|
2013-09-09 14:31:18 -07:00 |
|
Stephen Twigg
|
cfbfa6b895
|
Add errors due to merge issues. Note, DebugIO re-introduced here but slated for possible removal in later commits.
|
2013-09-05 19:22:34 -07:00 |
|
Stephen Twigg
|
e23e8e3850
|
Merge branch 'master' into chisel-v2
Conflicts:
src/main/scala/memserdes.scala
|
2013-09-05 16:17:34 -07:00 |
|
Stephen Twigg
|
d896ccbd43
|
Merge branch 'master' into chisel-v2
Conflicts:
src/main/scala/htif.scala
|
2013-09-05 16:11:53 -07:00 |
|
Stephen Twigg
|
f27c0fb010
|
Merge commit '2bd4a66eee572252ba6250f9bddada51657fc379' into chisel-v2
|
2013-09-05 15:01:56 -07:00 |
|
Stephen Twigg
|
69daae0dae
|
Add dependency resolvers to build.scala to fix build script
|
2013-09-05 14:56:41 -07:00 |
|
Yunsup Lee
|
2c47b4388a
|
push rocket
|
2013-08-26 14:54:49 -07:00 |
|
Andrew Waterman
|
b9f6e1a7ec
|
Don't update BTB when garbage was fetched
|
2013-08-26 14:53:04 -07:00 |
|
Yunsup Lee
|
9003bc2614
|
push rocket
|
2013-08-24 22:42:57 -07:00 |
|
Yunsup Lee
|
44e92edf92
|
fix scr parameterization bug
|
2013-08-24 22:42:51 -07:00 |
|
Yunsup Lee
|
d0674af13f
|
forgot to push riscv-rocket
|
2013-08-24 22:15:38 -07:00 |
|
Andrew Waterman
|
3895b75a56
|
Support non-power-of-2 BTBs; prefer invalid entries
|
2013-08-24 17:33:11 -07:00 |
|
Yunsup Lee
|
ba9bbc27df
|
apply same change to fpga top-level
|
2013-08-24 15:50:03 -07:00 |
|
Yunsup Lee
|
76cd90fc01
|
parameterize number of SCRs
|
2013-08-24 15:47:42 -07:00 |
|
Yunsup Lee
|
2ca5127785
|
parameterize number of SCRs
|
2013-08-24 15:47:14 -07:00 |
|
Yunsup Lee
|
694ebd65cf
|
push uncore
|
2013-08-24 15:24:25 -07:00 |
|
Yunsup Lee
|
b01fe4f6aa
|
fix memserdes bit ordering
|
2013-08-24 15:24:17 -07:00 |
|
Andrew Waterman
|
daf23b8f79
|
Add early out to multiplier
|
2013-08-24 14:44:23 -07:00 |
|
Andrew Waterman
|
67f80ba4b2
|
Stall div/mul writeback until WB slot is free
|
2013-08-24 14:44:17 -07:00 |
|
Andrew Waterman
|
d1b5076fee
|
Don't update BTB when garbage was fetched
|
2013-08-24 14:44:11 -07:00 |
|
Andrew Waterman
|
52e31f3298
|
Bypass scoreboard updates
This reduces div/mul/D$ miss latency by 1 cycle.
|
2013-08-24 14:44:04 -07:00 |
|
Andrew Waterman
|
d4a0db4575
|
Reflect ISA changes
|
2013-08-24 14:43:55 -07:00 |
|
Yunsup Lee
|
0884bc9789
|
fix DRAMSideLLCNull entries
|
2013-08-24 13:20:38 -07:00 |
|
Yunsup Lee
|
1e3ac0afa9
|
back to NTILES=1
|
2013-08-24 13:10:30 -07:00 |
|
Henry Cook
|
9aff60f340
|
whitespace error in build.sbt
|
2013-08-21 16:16:42 -07:00 |
|
Henry Cook
|
dc53529156
|
added resolver, bumped chisel dependency
|
2013-08-21 16:00:51 -07:00 |
|
Henry Cook
|
6aa500fc16
|
dont make assumptions about default project name when invoking sbt
|
2013-08-20 12:56:01 -07:00 |
|
Henry Cook
|
b06d33da2f
|
Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes
|
2013-08-19 19:54:41 -07:00 |
|
Henry Cook
|
ff7b486006
|
standardized sbt build
|
2013-08-15 18:13:19 -07:00 |
|
Henry Cook
|
85e5ce046f
|
pulled submodule commits, uncore sbt standardized
|
2013-08-15 17:07:13 -07:00 |
|
Henry Cook
|
6b20556661
|
Merge branch 'chisel-v2' of github.com:ucb-bar/reference-chip into chisel-v2
Conflicts:
chisel
riscv-hwacha
riscv-rocket
uncore
|
2013-08-15 16:39:30 -07:00 |
|
Henry Cook
|
784e017bae
|
Final Reg standardization
|
2013-08-15 16:37:58 -07:00 |
|
Henry Cook
|
ae02ebd153
|
Merge branch 'chisel-v2' of github.com:ucb-bar/riscv-rocket into chisel-v2
Conflicts:
src/core.scala
src/ctrl.scala
src/dpath_util.scala
src/fpu.scala
src/nbdcache.scala
src/tile.scala
|
2013-08-15 16:35:27 -07:00 |
|
Henry Cook
|
b80f45f8f2
|
Merge branch 'chisel-v2' of github.com:ucb-bar/uncore into chisel-v2
Conflicts:
src/main/scala/llc.scala
src/main/scala/slowio.scala
|
2013-08-15 16:22:12 -07:00 |
|
Henry Cook
|
3763cd0004
|
standardizing sbt build conventions
|
2013-08-15 15:57:16 -07:00 |
|
Henry Cook
|
3a266cbbfa
|
final Reg changes
|
2013-08-15 15:28:15 -07:00 |
|
Henry Cook
|
17d404b325
|
final Reg changes
|
2013-08-15 15:27:38 -07:00 |
|
Henry Cook
|
9b70ecf546
|
Reg standardization
|
2013-08-13 17:53:19 -07:00 |
|
Henry Cook
|
1308c08baa
|
Reg standardization
|
2013-08-13 17:52:53 -07:00 |
|
Henry Cook
|
b570435847
|
Reg standardization
|
2013-08-13 17:50:02 -07:00 |
|
Henry Cook
|
7ff4126d04
|
Abstracted UncachedTileLinkIOArbiters
|
2013-08-13 00:01:11 -07:00 |
|