19656e4abe
make sure to generate release from clean coh state on probe miss
2015-09-30 16:58:18 -07:00
833909a2b5
Chisel3 compatibility fixes
2015-09-30 14:36:26 -07:00
a7c908cb83
Don't declare Reg inside of when
...
We haven't yet decided what the Chisel3 semantics for this will be.
2015-09-30 12:43:36 -07:00
2f3d15675c
fix DataArray writemask in L1D
2015-09-28 16:02:39 -07:00
f8a7a80644
Make perf counters optional
2015-09-28 13:55:23 -07:00
5e88ead984
Add pseudo-ops to instructions.scala
2015-09-28 11:52:27 -07:00
b93a94597c
Remove needless control logic
2015-09-27 13:31:52 -07:00
4bda6b6757
fix bug in tlb refill
2015-09-26 21:27:36 -07:00
6bf8f41cef
make sure passthrough requests are treated as vm_enabled = false
2015-09-26 20:29:51 -07:00
c3fff12ff0
Revert "replace remaining uses of Vec.fill"
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This reverts commit f7a0d125e83f8ca59d9913bb1db79cef5a6d344a.
2015-09-25 17:09:06 -07:00
0bfb2962a6
Assume coh.isRead returns true for store-conditional
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This requires an uncore update.
2015-09-25 15:26:11 -07:00
a66bdb1956
replace remaining uses of Vec.fill
2015-09-24 17:53:26 -07:00
9eb988a4c6
make sure access to invalid physical address treated as exception
2015-09-22 10:11:43 -07:00
16c748576a
don't mux data_word_bypass between IOMSHR and cache
2015-09-22 10:10:57 -07:00
d89bcd3922
modify csr file to bring in line with HTIF changes
2015-09-22 10:10:57 -07:00
382faba4a6
Implement bypassing L1 data cache for MMIO
2015-09-22 10:10:57 -07:00
e72e5a34b5
Fix storage of SP values in DP registers
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The SFMA was zero-extending the SP value to 65 bits, rather than filling
the upper 32 bits with 1s. This meant that an FSD + FLD of that register
would not restore the value properly.
Also, minor code cleanup.
2015-09-21 12:20:44 -07:00
76bf1da310
[commitlog] zero-extend SP write-back values
2015-09-15 16:47:26 -07:00
3b48d8569c
[commitlog] don't print out writebacks to x0
2015-09-15 16:47:26 -07:00
e22bf02a80
[commitlog] CSR's cycle optionally set to instret
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- Allows debugging Rocket against Spike by having timer interrupts
occur in the same place in the instruction stream for both.
2015-09-15 16:47:26 -07:00
7d14abf262
[commitlog] Added privilege-level to output
2015-09-15 16:47:24 -07:00
53a02a62c8
[commitlog] Fix sp/dp bug in FPU writeback
2015-09-15 16:46:47 -07:00
d630a03857
[commitlog] Added FP instructions to the commitlog
2015-09-15 15:59:13 -07:00
91458bef1c
[commitlog] Initial commit log for integer working
2015-09-15 15:59:03 -07:00
78b2e947de
Chisel3 compatibility fixes
2015-09-11 15:43:07 -07:00
1718333f83
Don't use Vec as lvalue
2015-08-05 15:29:33 -07:00
546205b174
Chisel3 compatibility: use >>Int instead of >>UInt
2015-08-05 15:29:03 -07:00
fb5524372d
bump scala to 2.11.6
2015-08-03 19:51:08 -07:00
d4c94c6566
Chisel3 has different Vec semantics
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Vec(a, b) := c doesn't modify a and b in chisel3.
2015-08-03 19:08:00 -07:00
c345d72af4
Chisel3: Flip order of := and <>
2015-08-03 18:53:09 -07:00
ef319edc84
Bits -> UInt
2015-08-02 21:03:42 -07:00
52fc34a138
Chisel3: bulk connect is not commutative
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We haven't decided if this is a FIRRTL limitation that we should relax,
or a backwards incompatibility we're forced to live with. Should make
for lively debate.
2015-08-01 21:11:25 -07:00
6c0e1e33ab
Purge UInt := SInt assignments
2015-07-31 15:42:10 -07:00
6d7cc37e87
Specify some uninferrable widths
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It's really scary that Chisel2 passed this stuff.
2015-07-31 14:23:52 -07:00
45cf64dbd7
Use UInt instead of Vec[Bool]
2015-07-31 04:59:45 -07:00
57930e8a26
Chisel3 compatibility potpourri
2015-07-30 23:53:02 -07:00
db7258f887
Add junctions to the possible managed dependency list.
2015-07-30 15:11:23 -07:00
d2a594fb57
new junctions repo has mem size constants
2015-07-29 18:05:54 -07:00
9d67ef4ee2
simplify .sbt files
2015-07-29 17:22:33 -07:00
ce161b83e3
Chisel3 compatibility: avoid subword assignment
2015-07-29 15:03:13 -07:00
c8c312e860
minor btb cleanup
2015-07-29 15:03:01 -07:00
a2fdcdcaef
Use Seq, not Iterable, when traversal order matters
2015-07-29 00:24:58 -07:00
431dd2219b
Another Bits -> BitPat
2015-07-28 20:13:56 -07:00
049fc8dc24
Chisel3 compatibility: use BitPat for don't-cares
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This one's hella ugly, but for the time being, idgaf.
2015-07-28 02:48:49 -07:00
f2dcc40e67
Chisel3 compatibility changes
2015-07-27 12:42:20 -07:00
ae73e3a997
Only instantiate div/sqrt unit if requested
2015-07-22 22:18:18 -07:00
e9433ee01e
Minor cleanup
2015-07-22 17:38:08 -07:00
b4e4ceed3d
Factor out some more hazard detection code
2015-07-22 15:52:13 -07:00
bd785e7d19
Factor out common hazard detection code
2015-07-22 15:46:20 -07:00
cc447c8110
Refactor pipeline RTL (merge ctrl + dpath into rocket)
2015-07-21 17:10:56 -07:00
Howard Mao
Andrew Waterman
Christopher Celio
Scott Beamer
Jim Lawson
Henry Cook