 Yunsup Lee
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309193dd07
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change llc size
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2012-07-24 14:10:29 -07:00 |
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Yunsup Lee
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7736405726
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fix bug in coherence hub, respect xact_rep.ready
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2012-07-23 20:56:55 -07:00 |
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Yunsup Lee
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d0e12c13f6
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fix bug in coherence hub, respect xact_rep.ready
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2012-07-23 20:56:55 -07:00 |
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Yunsup Lee
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6541cf22a4
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fix bug in coherence hub, respect xact_rep.ready
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2012-07-23 20:56:55 -07:00 |
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Yunsup Lee
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f4e3e72ad1
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hoist HTIF_WIDTH out to consts
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2012-07-23 17:30:04 -07:00 |
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 Andrew Waterman
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a21c355114
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fix htif split request/response
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2012-07-23 17:15:16 -07:00 |
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Andrew Waterman
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df8aff0906
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don't dequeue probe queue during reset
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2012-07-22 21:05:52 -07:00 |
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Andrew Waterman
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c6ac836581
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don't dequeue probe queue during reset
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2012-07-22 21:05:52 -07:00 |
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Andrew Waterman
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938effc053
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don't dequeue probe queue during reset
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2012-07-22 21:05:52 -07:00 |
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Yunsup Lee
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379f021359
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change ioHTIF interface between the tile/uncore boundary to cope with asynchrony
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2012-07-22 18:26:02 -07:00 |
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Yunsup Lee
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c892950bf1
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hoist out uncore as its own component
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2012-07-22 17:48:17 -07:00 |
|
 Huy Vo
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0a97d6ab4d
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type casting
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2012-07-18 13:03:35 -07:00 |
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Andrew Waterman
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d01e70c672
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decouple all interfaces between tile and top
also, add an "incoherent" bit to tilelink to indicate no probes needed
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2012-07-17 22:55:40 -07:00 |
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Andrew Waterman
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0258dfb23f
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decouple all interfaces between tile and top
also, add an "incoherent" bit to tilelink to indicate no probes needed
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2012-07-17 22:55:40 -07:00 |
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Andrew Waterman
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f42c6afed2
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decouple all interfaces between tile and top
also, add an "incoherent" bit to tilelink to indicate no probes needed
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2012-07-17 22:55:40 -07:00 |
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Andrew Waterman
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4e44ed7400
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allow back pressure on IPI requests
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2012-07-17 22:55:40 -07:00 |
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Yunsup Lee
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f633a55722
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fix dcache tag array size
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2012-07-16 22:19:03 -07:00 |
|
 Andrew Waterman
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e496cd7584
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use Mem to implement queues to speed things up
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2012-07-13 21:48:05 -07:00 |
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Huy Vo
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a79747a062
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INPUT/OUTPUT orderring swapped
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2012-07-12 18:16:57 -07:00 |
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Huy Vo
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18bc14058b
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INPUT/OUTPUT orderring swapped
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2012-07-12 18:16:57 -07:00 |
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Huy Vo
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fd95159837
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INPUT/OUTPUT orderring swapped
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2012-07-12 18:16:57 -07:00 |
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Andrew Waterman
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bac82762d3
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use only one (wide) tag ram for set assoc. caches
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2012-07-12 14:50:12 -07:00 |
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Andrew Waterman
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62a3ea4113
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fix some LLC bugs
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2012-07-11 17:56:39 -07:00 |
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Andrew Waterman
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0aa33bf909
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fix some LLC bugs
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2012-07-11 17:56:39 -07:00 |
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Andrew Waterman
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429fcbed8e
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fix some LLC bugs
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2012-07-11 17:56:39 -07:00 |
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Andrew Waterman
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1ebfeeca8a
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add L2$
It still has performance bugs but no correctness bugs AFAIK.
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2012-07-10 05:23:29 -07:00 |
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Andrew Waterman
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66cf690261
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add L2$
It still has performance bugs but no correctness bugs AFAIK.
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2012-07-10 05:23:29 -07:00 |
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Andrew Waterman
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f645fb4dd7
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add L2$
It still has performance bugs but no correctness bugs AFAIK.
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2012-07-10 05:23:29 -07:00 |
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Andrew Waterman
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5035374f36
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update to new chisel
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2012-07-08 17:59:41 -07:00 |
|
 Andrew Waterman
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39d198ecdc
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fix htif handling of large memory reads
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2012-06-26 19:12:11 -07:00 |
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Andrew Waterman
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4e5f874266
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update to new chisel/hwacha
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2012-06-08 00:13:14 -07:00 |
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Huy Vo
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166b857055
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ioDecoupled -> FIFOIO, ioPipe -> PipeIO
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2012-06-06 18:22:56 -07:00 |
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Huy Vo
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0c6bade592
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ioDecoupled -> FIFOIO, ioPipe -> PipeIO
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2012-06-06 18:22:56 -07:00 |
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Huy Vo
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a99cebb483
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ioDecoupled -> FIFOIO, ioPipe -> PipeIO
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2012-06-06 18:22:56 -07:00 |
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Huy Vo
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9b3161920f
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moving util out into Chisel standard library
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2012-06-06 12:51:26 -07:00 |
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Huy Vo
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f2942f79f9
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moving util out into Chisel standard library
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2012-06-06 12:51:26 -07:00 |
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Huy Vo
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04304fe788
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moving util out into Chisel standard library
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2012-06-06 12:51:26 -07:00 |
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Huy Vo
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c975c21e44
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views removed
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2012-06-06 12:51:26 -07:00 |
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Andrew Waterman
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943b6d0616
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remove debug println
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2012-06-06 02:48:48 -07:00 |
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Andrew Waterman
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7f6319047e
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update to new scala/chisel/Mem
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2012-06-06 02:47:22 -07:00 |
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Huy Vo
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6f2f1ba21c
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removing wires
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2012-05-24 10:42:39 -07:00 |
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Huy Vo
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0208e9f95e
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removing wires
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2012-05-24 10:42:39 -07:00 |
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Huy Vo
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7408c9ab69
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removing wires
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2012-05-24 10:42:39 -07:00 |
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Huy Vo
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181b20d69c
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working vec unit with pvfb
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2012-05-24 10:38:14 -07:00 |
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Andrew Waterman
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faee45bf4c
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fix setpcr/clearpcr not writing rd
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2012-05-21 07:25:35 -07:00 |
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Yunsup Lee
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c9602a0d2e
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fix vector control decode bug
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2012-05-15 10:26:37 -07:00 |
|
 Gage W Eads
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d0bc995c88
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Fixed IRQ_IPI -> IRQ_TIMER typo
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2012-05-14 22:25:12 -07:00 |
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Andrew Waterman
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a2f6d01c1b
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add programmable coreid register
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2012-05-09 03:09:22 -07:00 |
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Andrew Waterman
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e0e1cd5d32
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add IPIs and an IPI test
IPIs are routed through the HTIF, which seems weird, but that makes it
so cores can bring each other out of reset with IPIs.
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2012-05-08 22:58:00 -07:00 |
|
 Henry Cook
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87cbae2c8a
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Removed defunct ioDmem
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2012-05-07 17:31:39 -07:00 |
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