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Commit Graph

5218 Commits

Author SHA1 Message Date
Eric Love
8a47c3f346 Make sure there's enough xact id bits 2016-03-16 13:49:30 -07:00
Matthew Naylor
04be438847 Avoid conflicting assigments to registers in timers. Give priority to start over stop. 2016-03-16 12:54:19 -07:00
Andrew Waterman
137b77d780 Merge pull request #4 from ucb-bar/chisel3
Work around Chisel3's lack of 0-width wires
2016-03-15 17:30:34 -07:00
Palmer Dabbelt
50f61687de Work around Chisel3's lack of 0-width wires
This is super ugly, but it's necessary to get Chisel3 to compile.  Note
that this still fails simulations in Chisel3, so it might be wrong.
2016-03-14 22:50:37 -07:00
Andrew Waterman
9dc0cbdfa4 WIP on privileged spec v1.9 2016-03-14 18:03:33 -07:00
Andrew Waterman
13dcb96b7f Update TLB interface
n.b. no need to set mprv, since prv = S.
2016-03-14 17:55:19 -07:00
Andrew Waterman
648437e7cb Merge pull request #70 from ucb-bar/add-rv32-support
Add RV32 test/configuration options
2016-03-14 17:06:39 -07:00
Eric Love
db09f310a1 Define MIFMasterTagBits as # bits a master can *use* in tag 2016-03-11 16:48:13 -08:00
Andrew Waterman
f2ded2721d Merge branch 'master' into add-rv32-support 2016-03-10 19:33:04 -08:00
Andrew Waterman
25091003af Add RV32 test/configuration options
These won't actually work until further commits.  Rocket RV32 support
is complete, but on the priv-1.9 branch.
2016-03-10 17:40:21 -08:00
Henry Cook
67e711844a index extraction bug 2016-03-10 17:37:40 -08:00
Palmer Dabbelt
e2185d40f6 Avoid right-shift by larger that the bit width
FIRRTL bails out on this.  There's an outstanding bug, this is just a
workaround.  See https://github.com/ucb-bar/firrtl/issues/69
2016-03-10 17:37:40 -08:00
Palmer Dabbelt
8c7e29eacd Avoid generating 0-width UInts
Chisel3 requires a 1-bit width to represent UInt(0).
2016-03-10 17:37:40 -08:00
Andrew Waterman
2eafc4c8f3 Extend AMOALU to support RV32 2016-03-10 17:32:23 -08:00
Andrew Waterman
c28d115b30 Chisel3 compatibility fix 2016-03-10 17:32:23 -08:00
Andrew Waterman
7ae44d4905 Add RV32 support 2016-03-10 17:32:00 -08:00
Andrew Waterman
82c595d11a Fix no-FPU elaboration of CSR file 2016-03-10 17:30:56 -08:00
Henry Cook
93773a4496 Refactor L2 transaction trackers to each be capable of processing Voluntary Writebacks.
To elide several races between reading and writing the metadata array for different types of transactions, all L2XactTrackers can now sink Voluntary Releases (writebacks from the L1 in the current implementation). These writebacks are merged with the ongoing transaction, and the merging tracker supplies an acknowledgment of the writeback in addition to its ongoing activities. This change involved another refactoring of the control logic for allocating new trackers and routing incoming Acquires and Releases. BroadcastHub uses the new routing logic, but still processes all voluntary releases through the VoluntaryReleaseTracker (not a problem because there are no metadata update races).

Closes #18
Closes #20
2016-03-10 17:14:34 -08:00
Andrew Waterman
67ad36d74a Merge pull request #69 from ucb-bar/fix-tabs
tabs are evil
2016-03-10 16:17:46 -08:00
Andrew Waterman
7a75a03123 tabs are evil 2016-03-10 14:18:56 -08:00
Howard Mao
3c9e63f5a5 don't make HTIF clock divider tied to backup memory 2016-03-09 14:58:20 -08:00
Andrew Waterman
3e721fe80b Merge pull request #2 from ucb-bar/chisel3
Pass a BitPat to Lookup
2016-03-06 04:27:52 -08:00
Palmer Dabbelt
bf06ba0d37 Pass a BitPat to Lookup
This is the only supported type of Lookup in Chisel 3.
2016-03-05 18:50:56 -08:00
Andrew Waterman
36f2e6504c Fix width of NastiROM rows, preventing out-of-range extraction 2016-03-03 16:57:16 -08:00
Andrew Waterman
bc15e8649e WIP on priv spec v1.9 2016-03-02 23:29:58 -08:00
Howard Mao
5e145515e1 fix some Chisel assertions 2016-03-02 14:50:49 -08:00
Henry Cook
7eef3393f1 fix bug resulting in different g_types on tail beats in L2CacheBank.io.inner.grant 2016-03-02 14:11:45 -08:00
Henry Cook
57370bdf49 first and last on HasTileLinkData 2016-03-02 14:11:39 -08:00
Colin Schmidt
9c7e5bc6c0 bump hardfloat, tools(tests & spike) for fcvt fix 2016-03-01 19:53:26 -08:00
Albert Magyar
a80b0e959d Add support for per-way cache metadata
Adds a new cache parameter (SplitMetadata) and an associated knob.

Closes #62
2016-03-01 13:03:24 -08:00
Palmer Dabbelt
4acdc67485 Add an assertion in the NastiIOTileLink converter
This uses an reorder queue but doesn't check to ensure that the data it fetches
from the queue is actually in the queue before using it.  It seems that during
correct operation this never breaks, but I'm trying to get the backup memory
port working again and this assertion fails with it enabled (without the
assertion the core just gets a bogus data beat dies).

Closes #16
2016-03-01 12:23:32 -08:00
Albert Magyar
ab30983aa9 Add support for per-way cache metadata
Exposes new parameter field SplitMetadata to determine whether the metadata array in a particular cache is stored in a single SeqMem or with one SeqMem per way.

Closes #14
2016-03-01 12:19:42 -08:00
Colin Schmidt
a9380a3dc1 bump hardfloat,uncore,chisel,tools(tests) for sqrt fix 2016-02-29 16:59:55 -08:00
Howard Mao
6d984273b7 finally fix all release assertions ... hopefully 2016-02-29 15:22:24 -08:00
Howard Mao
760893e448 add makefile for float_fix and comlog tools 2016-02-29 11:24:53 -08:00
Howard Mao
be8a411f9c get rid of axe submodule and move toaxe.py script to scripts 2016-02-29 10:59:19 -08:00
John Wright
ba96ad2b38 Move N_CORES and MMIO_BASE to SCRFile instance in RocketChip 2016-02-27 16:24:45 -08:00
John Wright
6095e7361e Move N_CORES and MMIO_BASE to SCRFile instance in RocketChip 2016-02-27 16:19:25 -08:00
Palmer Dabbelt
7fa38b5624 Merge pull request #68 from ucb-bar/test-and-fix-backup-mem
Fix the backup memory port
2016-02-27 12:19:55 -08:00
Palmer Dabbelt
a0f3189c74 Change MIF_DATA_BITS back to 64
It turns out the Chisel C++ backend can't emit correct initialization
code for a 128 bit wide NastiROM.  Rather than trying to fix Chisel, I'm
just going to hack up the backup memory port Verilog harness a bit more
to make it work.

Note that the backup memory port Verilog already couldn't take arbitrary
parameters for MIF_*, so it's not like we're losing any flexibility
here.
2016-02-27 11:43:44 -08:00
Palmer Dabbelt
9ea8c4e781 Add an 8-channel backup memory port config
Now that the backup memory port works I want to test it.
2016-02-27 10:56:13 -08:00
Palmer Dabbelt
7319f430d0 Fix the backup memory port on multiple-channel configs
The backup memory port doesn't work on multi-channel configurations, it
just screws up the Nasti tag bits.  This patch always instantiates a
single-channel backup memory port, which relies on the memory channel
selector to only enable a single memory channel when the backup memory
port is enabled.  There are some assertions to make sure this happens,
as otherwise memory gets silently corrupted.

While this is a bit of a hack, the backup memory port will be going away
soon so I don't want to spend a whole lot of time fixing it.  The
generated hardware is actually very similar: we used to elaborate a
Nasti arbiter inside the backup memory support, now there's one outside
of it instead.
2016-02-27 10:47:52 -08:00
Palmer Dabbelt
7c0c48fac4 Resurrect the backup memory port
We need this to work for our chip, and it's not been tested in a long
time in upstream -- it didn't even used to build since the Nasti
conversion.  This makes a few changes:

 * Rather than calling the backup memory port parameters MEM_*, it calls
   them MIF_* (to match the MIT* paramater objects).  A new name was
   necessary because the Nasti stuff is now dumped as MEM_*, which has
   similar names but incompatible values.

 * p(MIFDataBits) was changed back to 128, as otherwise the backup
   memory port doesn't work (it only send half a TileLink transaction).
   64 also causes readmemh to bail out, but changing the elf2hex parameters
   works around that.

 * A configuration was added that enabled the backup memory port in the
   tester.  While this is kind of an awkward way to do it, I want to
   make sure I can start testing this regularly and this makes it easy to
   integrate.
2016-02-27 10:46:56 -08:00
Colin Schmidt
68a49c7700 fetch rocketchip_addons during regression submodule step 2016-02-26 11:05:41 -08:00
Palmer Dabbelt
8c73d10fe1 Support SCR address generation with __OFFSET at the end 2016-02-25 21:57:37 -08:00
Palmer Dabbelt
ebffd69b8e Provide both __OFFSET and __PADDR for SCR entries
This was recently changed to write out physical addresses for SCR file entries,
but to bring up the chip we need SCR offsets so we can write the uncore SCR
file over HTIF.  This changes the map generator to generate both.

Without this change things happened to work anyway because the high bits were
getting dropped by the SCR file.
2016-02-25 21:48:32 -08:00
Andrew Waterman
640204b221 Merge pull request #66 from ucb-bar/rocc-ptw-refactoring
RoCC PTW refactoring
2016-02-25 18:01:01 -08:00
Andrew Waterman
091782ad27 Merge pull request #29 from ucb-bar/rocc-ptw-refactoring
RoCC PTW refactoring
2016-02-25 17:57:22 -08:00
Yunsup Lee
a2381d2faf RoCC PTW refactoring 2016-02-25 17:26:42 -08:00
Yunsup Lee
15ac4d317f RoCC PTW refactoring 2016-02-25 17:15:38 -08:00