Wesley W. Terpstra
a814cba04f
spi: put a request buffer infront of SPI
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This will prevent SPI from blocking other pbus requests.
2017-08-19 12:52:10 -07:00
Wesley W. Terpstra and GitHub
d973c659eb
uart: make it easy to simulate large text printouts ( #33 )
2017-08-10 16:32:48 -07:00
Wesley W. Terpstra
fced2323bd
spi: remove removed sink arg
2017-07-26 16:02:44 -07:00
Wesley W. Terpstra and GitHub
66b2fd11bd
vc707 axi enhancements ( #24 )
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1 - Print AXI-ID mappings
2 - Use half as many Deinterleaver buffers for the L2 backside
3 - Limit the Q depth on the PCIe control port to 2 (was 1584!)
2017-06-30 12:36:33 -07:00
Wesley W. Terpstra
886680af49
mig: fix MemoryDevice to use 'reg' properly
2017-06-29 13:41:30 -07:00
Wesley W. Terpstra and GitHub
a8e20f447c
spi: include mem region ( #23 )
2017-06-28 17:46:45 -07:00
Wesley W. Terpstra and GitHub
3d8c502fce
diplomacy: add reg-names to devices ( #22 )
2017-06-28 17:45:18 -07:00
Wesley W. Terpstra and GitHub
90d3931f5a
spi: add dts ranges field for memory mapped spi ( #19 )
2017-06-14 17:06:55 -07:00
Wesley W. Terpstra and GitHub
0ca609d324
vc707axi: track rocketchip API changes ( #16 )
2017-06-02 15:56:18 -07:00
Wesley W. Terpstra and GitHub
0f8722f80c
uart: power-on with the right divider for the design ( #15 )
2017-05-13 23:38:20 -07:00
Wesley W. Terpstra and GitHub
9c8fe44670
Merge pull request #14 from sifive/async-pcie
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Async PCIe
2017-05-12 23:15:14 -07:00
Wesley W. Terpstra
c4c158963c
vc707mig: use an external ibuf
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This makes it possible to also drive a PLL of our own from the crystal.
2017-05-12 23:07:10 -07:00
Wesley W. Terpstra
0ed21ba465
xilinxvc707pciex1: push to a dedicated clock domain
2017-05-12 23:02:44 -07:00
Wesley W. Terpstra and GitHub
b3f9607512
xilinx mig: put a buffer infront of the controller ( #13 )
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This makes placement of the L2 and DDR controller easier.
2017-05-11 11:50:07 -07:00
Wesley W. Terpstra and GitHub
178ac84b59
xilinxvc707pciex1: better wrapper for AXI4-Lite control node ( #12 )
2017-05-08 01:08:37 -07:00
Wesley W. Terpstra
a24fa9b444
axi4: switch to new pipelined converters
2017-04-26 13:10:50 -07:00
Wesley W. Terpstra
062203ae18
xilinx pcie: add the high PCIe address bits (physical path)
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The format is taken from here:
http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
2017-03-02 21:22:41 -08:00
Wesley W. Terpstra and GitHub
64bff44462
Merge pull request #4 from sifive/periphery-keys
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DTS
2017-03-02 21:00:44 -08:00
Wesley W. Terpstra and Henry Cook
46aa6b0ac4
devices: include DTS meta-data
2017-03-02 20:39:30 -08:00
Wesley W. Terpstra and Henry Cook
baccd5ada2
devices: create periphery keys for all devices
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Standardize how they are connected to the periphery bus
2017-03-02 20:39:25 -08:00
Wesley W. Terpstra
88e4c8ee20
xilinx mig: track changes in rocket-chip
2017-02-03 18:17:58 -08:00
Wesley W. Terpstra
c010a1557a
sifive-blocks: trust diplomacy to get names right
2017-02-01 13:53:54 -08:00
Wesley W. Terpstra
535be3e976
spi: work around ucb-bar/chisel3#472
2017-01-31 14:03:14 -08:00
Wesley W. Terpstra
5b6760394d
xilinx ip: adjust to new diplomacy API
2017-01-30 11:33:30 -08:00
Wesley W. Terpstra
d61d86e084
xilinx pcie: put buffers before the outputs to the controller
2017-01-20 22:38:27 -08:00
Wesley W. Terpstra
c68e44ec55
mig: track change to Blind port API in rocket
2017-01-19 19:53:03 -08:00
Wesley W. Terpstra
45c491cd69
LazyModule: provide Parameters
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This tracks PR #478 in rocketchip.
2016-12-07 13:21:20 -08:00
Wesley W. Terpstra
1443834186
xilinx pcie: bytes, not bits
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This bug amazingly compiled correctly and ran correctly!
It was saved by the AXIFragmenter which turned the "narrow burst" into
individual beats that then got converted to 64b in TileLink land via
inspection of the mask bits.
The consequence is that AXI bus mastering proceeded at one word per
DDR round-trip. Now it is one cache line per DDR round-trip. When we
get L2 back in the design, it should really fly!
2016-12-06 16:13:12 -08:00
Wesley W. Terpstra
ca7555bd4d
RegMapFIFO: amoor.w can do thread-safe TX
2016-12-02 17:48:17 -08:00
