riscv/rocket-chip
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  • 08d2c13330 Fixed btb/icache bugs regarding resp mask, fw==1 Christopher Celio 2014-10-20 18:45:23 -07:00
  • 044b19dbc1 Compiles and elaborates, does not pass asm tests Henry Cook 2014-10-15 11:46:35 -07:00
  • 91efdc379b Merge remote-tracking branch 'origin/master' into ss-frontend Christopher Celio 2014-10-14 18:10:29 -07:00
  • 7bb7299018 Don't pollute BTB with PC+4 target predictions Andrew Waterman 2014-10-14 17:28:37 -07:00
  • 86bdbd6535 new tshrs, compiles but does not elaborate Henry Cook 2014-10-07 22:33:10 -07:00
  • 1b31931981 Merge pull request #2 from wasserfuhr/patch-1 Yunsup Lee 2014-10-07 17:02:55 -07:00
  • 9b41ad92ba Update README.md RainerWasserfuhr 2014-10-08 01:46:48 +02:00
  • f15baeea49 fix markdown for webpage Yunsup Lee 2014-10-07 03:54:30 -07:00
  • 5ca7f08226 change rocket submodule Yunsup Lee 2014-10-07 03:19:48 -07:00
  • e1b8f69cb5 change submodule pointers to https Yunsup Lee 2014-10-07 03:16:20 -07:00
  • 447761b06c fix typo in README Yunsup Lee 2014-10-07 02:09:17 -07:00
  • 91f211f766 updates to README Yunsup Lee 2014-10-07 02:05:20 -07:00
  • 702ddabe26 add ExampleSmallConfig for README Yunsup Lee 2014-10-07 02:05:10 -07:00
  • ae9b78d9ef add what/how explanation to README Yunsup Lee 2014-10-07 02:07:39 -07:00
  • 5f55ded723 bump fpga submodule Scott Beamer 2014-10-03 16:52:05 -07:00
  • 06bc6a45db move fpga repo to git@ from https Scott Beamer 2014-10-03 16:49:47 -07:00
  • 23ae6893ad bump chisel Henry Cook 2014-10-03 01:58:00 -07:00
  • e25d420155 Improve ChiselConfig composability; bump chisel Yunsup Lee 2014-10-06 13:43:40 -07:00
  • 73eac94a65 Added "findBy" function to allow grouping parameters by location (e.g. L1D vs L1I), rather than grouping by field (e.g. NSets vs NWays) Yunsup Lee 2014-10-06 13:40:35 -07:00
  • f97a801d60 Parameter API update Henry Cook 2014-10-02 16:49:10 -07:00
  • 122733b3a9 file name consistency Henry Cook 2014-09-30 16:28:54 -07:00
  • a9d72aac2a bump rocket Henry Cook 2014-09-25 19:24:27 -07:00
  • 0b5f23a209 Streamlined uncore for release Henry Cook 2014-09-24 18:34:04 -07:00
  • 59eb7d194d Finalize superscalar btb. Christopher Celio 2014-10-03 16:08:08 -07:00
  • cde7c9d869 simplify CSR decoding code Andrew Waterman 2014-10-03 14:31:01 -07:00
  • 99614e37aa Merge remote-tracking branch 'origin/master' into ss-frontend Christopher Celio 2014-10-03 04:22:58 -07:00
  • 394eb38a96 temp; converted voluntary wb tracker Henry Cook 2014-10-03 01:06:33 -07:00
  • dc1a61264d initial version, acts like old hub Henry Cook 2014-09-30 14:48:02 -07:00
  • d735f64110 Parameter API update Henry Cook 2014-10-02 16:47:35 -07:00
  • 655f9ae1af Merge pull request #2 from ccelio/master Andrew Waterman 2014-09-30 17:12:15 -07:00
  • 6c18cd9559 add new fpga-zynq as submodule Yunsup Lee 2014-09-30 09:31:38 -07:00
  • 9cc35dee9a Returned history update to fetch. Christopher Celio 2014-09-29 21:41:07 -07:00
  • 8ccd07cfeb Moved updating global history from fetch to decode. Christopher Celio 2014-09-28 05:16:36 -07:00
  • 681b43f398 Bug fixes with global history register. Christopher Celio 2014-09-26 10:39:57 -07:00
  • a71bdbbc54 Update history register in fetch speculatively Christopher Celio 2014-09-19 15:05:45 -07:00
  • f917810061 Removed RocketCoreParameters from use. Christopher Celio 2014-09-26 05:14:50 -07:00
  • 868e747656 Factored out Rocket specifics from CoreParameters Christopher Celio 2014-09-25 18:52:58 -07:00
  • 7a28d2b47c forgot to move more hwacha stuff out in rocket-chip Yunsup Lee 2014-09-25 15:33:40 -07:00
  • 8eb64205f5 bug fix for nbdcache s2_data Henry Cook 2014-09-25 11:59:19 -07:00
  • b55c38cdc7 Remove spurious vec consts Henry Cook 2014-09-24 22:17:28 -07:00
  • 70b0f9fd4d error out for PCWM-L, port width mismatch Yunsup Lee 2014-09-25 06:43:03 -07:00
  • 15fb4730ec Add BuildTile parameter for Tile Adam Izraelevitz 2014-09-24 13:08:45 -07:00
  • 7398b00d93 dir supplied by function Henry Cook 2014-09-24 12:04:11 -07:00
  • db4de7b806 bump chisel Henry Cook 2014-09-24 12:01:56 -07:00
  • 5a840c5520 support for multiple tilelink paramerterizations in same design Henry Cook 2014-09-24 11:34:16 -07:00
  • e2ed81dcd2 push chisel Yunsup Lee 2014-09-25 06:50:05 -07:00
  • eb384f6461 new RocketChipBackend implementation Donggyu Kim 2014-09-23 17:37:54 -07:00
  • f2ca887de3 better fpga configs Scott Beamer 2014-09-23 17:05:14 -07:00
  • 4fe48f5a0a bump chisel Donggyu Kim 2014-09-23 16:56:32 -07:00
  • 60d90f5230 recover collectNodesIntoComp in Backends.scala Donggyu Kim 2014-09-23 00:23:54 -07:00
  • a53091b40f remove collectNodesIntoComp from Backends.scala Donggyu Kim 2014-09-22 17:08:33 -07:00
  • 1a101f8de5 don't use latches on mem ports for fpga Scott Beamer 2014-09-22 16:42:33 -07:00
  • f4e6cd75ab turn off fpu for default fpga config. a larger fpga can use defaultconfig Scott Beamer 2014-09-22 16:42:06 -07:00
  • fefa560017 Change addons subproject to use .addons-dont-touch directory instead of addons Stephen Twigg 2014-09-18 21:22:13 -07:00
  • 69d765744c Adjustments to the build structure (see below) Stephen Twigg 2014-09-18 16:24:19 -07:00
  • 3b9624277a normalize rocket-chip to reference-chip Yunsup Lee 2014-09-25 06:45:09 -07:00
  • 7571695320 Removed broken or unfinished modules, new MemPipeIO converter Henry Cook 2014-09-24 15:11:24 -07:00
  • 3e256439c9 Add abstract class Tile Adam Izraelevitz 2014-09-24 13:04:20 -07:00
  • 82fe22f958 support for multiple tilelink paramerterizations in same design Henry Cook 2014-09-24 11:14:36 -07:00
  • 53b8d7b031 use new coherence methods in l2, ready to query dir logic Henry Cook 2014-07-13 22:29:15 -07:00
  • 149d51d644 more coherence API cleanup Henry Cook 2014-07-10 17:10:32 -07:00
  • faed47d131 use thunk for dir info Henry Cook 2014-07-10 17:01:19 -07:00
  • f7b1e23ead functional style on MuxBundle Henry Cook 2014-07-10 16:59:48 -07:00
  • 180d3d365d Expanded front-end to support superscalar fetch. Christopher Celio 2014-09-17 14:24:03 -07:00
  • 6495d0e6f7 bump rocket,uncore Yunsup Lee 2014-09-17 11:25:58 -07:00
  • f249da1803 update README Yunsup Lee 2014-09-17 11:25:14 -07:00
  • 238f7761f6 update README Yunsup Lee 2014-09-17 11:23:25 -07:00
  • 041a362943 push chisel Yunsup Lee 2014-09-17 10:49:03 -07:00
  • 221007595b allow BACKEND/CONFIG be environment variables Yunsup Lee 2014-09-17 10:48:56 -07:00
  • 484648d9c7 Changed CONFIG from a recursively expanded variable to a conditionally assigned variable, allowing users to define CONFIG external to Makefile Adam Izraelevitz 2014-09-15 12:53:19 -07:00
  • ef2e96211c bump chisel/hardfloat/rocket/uncore Yunsup Lee 2014-09-12 18:07:40 -07:00
  • 09de2e2794 compute number of outstanding misses for DRAMSideLLCNull Yunsup Lee 2014-09-12 18:06:20 -07:00
  • 8abf62fae3 add LICENSE Yunsup Lee 2014-09-12 18:06:41 -07:00
  • 25180b71f7 add LICENSE Yunsup Lee 2014-09-12 15:36:42 -07:00
  • 49b027db2c forgot to add LICENSE file Yunsup Lee 2014-09-12 15:36:29 -07:00
  • 0b51d70bd2 add LICENSE Yunsup Lee 2014-09-12 15:31:38 -07:00
  • e40a6fdd64 more tweaks to README Yunsup Lee 2014-09-12 10:22:00 -07:00
  • c57dea415c fix markdown Yunsup Lee 2014-09-12 10:18:14 -07:00
  • 1cfd9f5a0e add LICENSE Yunsup Lee 2014-09-12 10:15:04 -07:00
  • 2367b7beb5 Added logic to sbt so that, for rocketchip, it will automatically include src/main/scala sources from subdirectories into the rocketchip top-level project not already handled by formal subprojects Stephen Twigg 2014-09-12 01:08:11 -07:00
  • 2c33852c52 final touches Yunsup Lee 2014-09-12 00:19:29 -07:00
  • 275b72368b add CONFIG to the name of simulator executable Yunsup Lee 2014-09-11 22:11:58 -07:00
  • c98afa1fea turn off DRAMSideLLC Yunsup Lee 2014-09-11 22:10:25 -07:00
  • b5a64487eb turn off DRAMSideLLC Yunsup Lee 2014-09-11 22:07:44 -07:00
  • f8d450b4e2 mark DRAMSideLLC as HasKnownBug Yunsup Lee 2014-09-11 22:06:03 -07:00
  • 9dfaf5459e bump hardfloat,riscv-tools Yunsup Lee 2014-09-11 03:08:21 -07:00
  • 5f8bd18fac Makefiles should be perfect Yunsup Lee 2014-09-11 02:53:46 -07:00
  • bb22ecc8b5 fix rocket interrupt issue Yunsup Lee 2014-09-11 02:52:05 -07:00
  • 086bb02c24 check RISCV envirnoment variable Yunsup Lee 2014-09-11 02:38:21 -07:00
  • a999c055ed Don't take an interrupt when EX stage PC is invalid Andrew Waterman 2014-09-11 01:46:42 -07:00
  • 02c08a156f generate consts.vh from chisel source Yunsup Lee 2014-09-10 17:14:55 -07:00
  • cfecd8832d tease out reference-chip specific stuff Yunsup Lee 2014-09-09 20:49:28 -07:00
  • 6b6bdd2b83 decommission Slave top-level module for fpga build Yunsup Lee 2014-09-08 00:23:15 -07:00
  • ddfd3ce968 further generalize fpga/vlsi builds Yunsup Lee 2014-09-08 00:21:57 -07:00
  • 3175a40509 add berkeley-hardfloat as submodule Yunsup Lee 2014-09-08 00:18:49 -07:00
  • 1e5b2f658f remove existing hardfloat repository Yunsup Lee 2014-09-07 23:45:47 -07:00
  • ae05125f29 Adjustements to top-level parameters and knobs for hwacha Henry Cook 2014-09-07 17:57:33 -07:00
  • 5eb5e9eaf5 Standardize ()=>Module(...) top-level Parameters Henry Cook 2014-09-07 17:54:41 -07:00
  • 4126678c9d Merge branch 'dse' Henry Cook 2014-09-06 06:59:14 -07:00
  • 5e26b4ab66 Merge branch 'dse' Henry Cook 2014-09-06 06:16:58 -07:00