riscv/rocket-chip
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Added logic to sbt so that, for rocketchip, it will automatically include src/main/scala sources from subdirectories into the rocketchip top-level project not already handled by formal subprojects

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Stephen Twigg 2014-09-12 01:08:11 -07:00
parent 2c33852c52
commit 2367b7beb5
1 changed files with 14 additions and 1 deletions
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15
project/build.scala
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@ -30,7 +30,20 @@ object BuildSettings extends Build {
lazy val hardfloat = Project("hardfloat", file("hardfloat"), settings = buildSettings) dependsOn(chisel)
lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(hardfloat)
lazy val rocket = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore)
lazy val rocketchip = Project("rocketchip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket)
val baselist = Vector("chisel", "uncore", "rocket", "hardfloat")
def show[A](in: Seq[A]) = in.map(_.toString).foldRight("")(_+" "+_)
def getsubdirs = {
val blacklist = (baselist ++ Vector("target", "project"))
IO.listFiles(file(".")) map (_.toString.split("/").last) filter (f=> !blacklist.contains(f)) filter (f=> !IO.listFiles(file(f+"/src/main/scala")).isEmpty)
}
val othersources = getsubdirs map (f=>s"${f}/src/main/scala") map (f=>file(f))
val addOtherFiles = Seq (
unmanagedSourceDirectories in Compile ++= othersources.toSeq
) // aggregate extra sources into rocketchip
lazy val rocketchip = Project("rocketchip", file("."), settings = buildSettings ++ chipSettings ++ addOtherFiles).dependsOn(chisel, hardfloat, uncore, rocket)
val elaborateTask = InputKey[Unit]("elaborate", "convert chisel components into backend source code")
val makeTask = InputKey[Unit]("make", "trigger backend-specific makefile command")