don't use latches on mem ports for fpga

2014-09-22 16:42:33 -07:00
parent f4e6cd75ab
commit 1a101f8de5
1 changed files with 1 additions and 1 deletions
--- a/fsim/fpga_mem_gen
+++ b/fsim/fpga_mem_gen
@ -6,7 +6,7 @@
 import sys
 import math

-use_latches = 1
+use_latches = False


 module_template = '''module %s(