riscv/rocket-chip
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bump chisel

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Donggyu Kim 2014-09-23 16:56:32 -07:00 committed by Yunsup Lee
parent 60d90f5230
commit 4fe48f5a0a
2 changed files with 2 additions and 2 deletions
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2
chisel

@ -1 +1 @@
Subproject commit d7e913088f840cff42d56920ab323c9b5f399b6f
Subproject commit e78ebbb858f3d7f426128aa85380723c2ab61064

2
src/main/scala/Backends.scala
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@ -62,7 +62,7 @@ class RocketChipBackend extends VerilogBackend
initMap += (c -> init)
}
transforms += {c => collectNodesIntoComp}
transforms += collectNodesIntoComp
transforms += addTopLevelPin
transforms += addMemPin
}