riscv/rocket-chip
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  • 3de9a04272 debug regression: until XLEN fix is merged into riscv-tests, have to explicitly state the XLEN Megan Wachs 2017-11-15 16:05:36 -0800
  • bd5fe5d22e Debug regression: have to say something about memory in order to run a simple test Megan Wachs 2017-11-03 16:13:25 -0700
  • 5df55d7911 debug regression: bump riscv-tools for riscv-tests fixes Megan Wachs 2017-11-03 15:16:23 -0700
  • 593839e0d5 Debug: add Debug regression to Travis regressions. Megan Wachs 2017-11-03 08:38:18 -0700
  • 4449dd0baa Debug regressions: Add necessary config scripts Megan Wachs 2017-11-03 08:26:03 -0700
  • e82328336e Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface. Megan Wachs 2017-04-11 20:03:34 -0700
  • b77b93b0b4 util: dontTouchPortsExcept Henry Cook 2017-10-02 19:34:51 -0700
  • 000cde2f8a Make ErrorDevice UNCACHEABLE instead of UNCACHED Andrew Waterman 2018-01-05 14:00:42 -0800
  • ad0b9a0b1b Reduce cases in which FENCE.I must flush D$ Andrew Waterman 2018-01-05 13:58:14 -0800
  • 4853d1355f rocket: dontTouch HellaCache.io.cpu.resp Henry Cook 2018-01-05 12:50:24 -0800
  • 847efde385 coreplex: dontTouch the tile_inputs wire Henry Cook 2018-01-05 12:47:41 -0800
  • f749e986cf coreplex: fix TL MMIO port example Wesley W. Terpstra 2018-01-05 12:27:18 +0100
  • 206892899f
         Merge pull request #1171 from freechipsproject/fix-msb-check Andrew Waterman 2018-01-03 12:06:18 -0800
  • 1bd343bcef
         Merge pull request #1156 from freechipsproject/has-tiles Henry Cook 2018-01-02 19:38:17 -0800
  • ee1a9485df Enforce physical-address canonicalization Andrew Waterman 2018-01-02 18:28:59 -0800
  • 7c9a1b0265 Correctly check for virtual-address canonicalization Andrew Waterman 2018-01-02 18:41:25 -0800
  • 320900f76c tile: BaseTileModule => BaseTileModuleImp Henry Cook 2018-01-02 17:55:54 -0800
  • b0e1bc3071 tile: cake reduction Henry Cook 2018-01-02 16:03:05 -0800
  • efe7165b54 tile: BaseTile refactor, pt 2 Henry Cook 2018-01-02 15:37:31 -0800
  • 1579ddb97e tile: removed RocketTileWrapper. RocketTile now HasCrossing. Henry Cook 2017-12-28 14:00:13 -0800
  • 1cd018546c tile: BaseTile refactor, pt 1 Henry Cook 2017-12-20 17:18:38 -0800
  • ba6dd160a3 diplomacy: allow access to sram Device info Henry Cook 2017-12-21 11:42:12 -0800
  • 7385c99435
         Bump chisel3 and firrtl to get bug fixes (#1163) Jack Koenig 2017-12-20 19:06:38 -0800
  • d9c5ec4f7b coreplex: HasTiles supplies def tileParams Henry Cook 2017-12-18 12:19:38 -0800
  • ddaeedf2d0 coreplex: make HasTiles more generic Henry Cook 2017-12-13 19:00:29 -0800
  • 9b82f1098d
         Merge pull request #1154 from freechipsproject/bump-sbt Henry Cook 2017-12-19 14:16:47 -0800
  • 895c4b9261
         Revert "ICache: stores to the ITIM have effects (shrinking valid ITIM data) (#1144)" (#1162) Henry Cook 2017-12-19 12:16:26 -0800
  • 74d9326ebc
         JTAG: Revert to Chisel._ for Issue 1160 (#1161) Megan Wachs 2017-12-18 21:02:31 -0800
  • a31ba2ea2e
         diplomacy: LazyModule factory uses ValName (#1159) Henry Cook 2017-12-18 15:40:30 -0800
  • 3df401eef7 Bump chisel3 and firrtl and bump sbt to version 1.0.4 Jack Koenig 2017-12-12 18:46:51 -0800
  • b914564a62 Move build.scala -> build.sbt Jack Koenig 2017-12-12 18:12:30 -0800
  • 0b2d200e91 Bump scala and sbt-site plugin versions. Jim Lawson 2017-12-12 12:43:10 -0800
  • 09160d0cd5
         Changed label for DCache and ICache error covers + take away exclusio… (#1155) Jacob Chang 2017-12-13 20:16:36 -0800
  • a542ae687e
         ICache: stores to the ITIM have effects (shrinking valid ITIM data) (#1144) Wesley W. Terpstra 2017-12-08 17:35:14 -0800
  • c2a0319dc4
         Merge pull request #1151 from freechipsproject/error-atoms Wesley W. Terpstra 2017-12-08 17:34:55 -0800
  • efc793d52e CloneModule: must be public to be used in pattern matches Wesley W. Terpstra 2017-12-08 14:57:08 -0800
  • 2ca03384ec diplomacy: skip anonymous class names Wesley W. Terpstra 2017-12-08 14:36:12 -0800
  • 588dacec17
         Bump Chisel and Firrtl (#1134) Jack Koenig 2017-12-08 14:22:18 -0800
  • 18b8a61775 Error device: require explicit control of atomic and transfer sizes Wesley W. Terpstra 2017-12-08 13:41:09 -0800
  • 6a0150aad7 Error device: mark executable to support testing erroneous I$ refill Wesley W. Terpstra 2017-12-08 12:38:06 -0800
  • 9cc37b8444
         Merge pull request #1150 from freechipsproject/fix-uncached-unaligned-fetch Gleb Gagarin 2017-12-08 11:02:44 -0800
  • 676110bc1f Add cover for a1ebe6da4d Andrew Waterman 2017-12-07 20:47:31 -0800
  • a1ebe6da4d Prevent frontend deadlock fetching from uncacheable memory Andrew Waterman 2017-12-07 18:56:06 -0800
  • ec3789b365
         Add Cross Cover Property Library (#1149) Jacob Chang 2017-12-07 18:46:10 -0800
  • 5c204f98d5
         When writing full words to ITIM, ECC errors are correctable (#1148) Andrew Waterman 2017-12-07 16:00:26 -0800
  • cfa819fc58
         Merge pull request #1142 from freechipsproject/fix-typo-in-cover-property-name Richard Xia 2017-12-04 15:10:05 -0800
  • 50de991f18 Fix typo in breakpoint cover property. Richard Xia 2017-12-04 14:04:24 -0800
  • b8098d18be
         diplomacy: remove the :=? operator in favour of magic :*=* (#1139) Wesley W. Terpstra 2017-12-01 18:28:37 -0800
  • dedf396915
         groundtest: connect the ibus to a fictitious master (#1140) Wesley W. Terpstra 2017-12-01 18:28:24 -0800
  • 71ddd797bf
         Merge pull request #1138 from freechipsproject/cover_tag_ecc_error_during_fence_i Henry Cook 2017-12-01 18:00:11 -0800
  • 7c2df9f0bf Cover the case when there is an ECC error in DCache data array during fence.i execution Gleb Gagarin 2017-12-01 16:28:28 -0800
  • 74bd61c556 Added coverage point to cover the case when ECC error happens during fence.i execution Gleb Gagarin 2017-12-01 15:50:31 -0800
  • 4bac8be483
         Merge pull request #1094 from freechipsproject/in-situ-unit-tests Wesley W. Terpstra 2017-12-01 13:27:30 -0800
  • 8781d2b2e7 diplomacy: provide a val name for all LazyModule constructions Wesley W. Terpstra 2017-12-01 11:27:54 -0800
  • a3e44375c6 ValName: 'lazy val' now also counts for providing a name Wesley W. Terpstra 2017-12-01 10:54:05 -0800
  • fe8d557751 PeripheryBus: automatically disappear when not used Wesley W. Terpstra 2017-11-30 16:34:46 -0800
  • 93c8010aca FrontBus: automatically disappear when not used Wesley W. Terpstra 2017-11-30 16:13:56 -0800
  • e489c4226e diplomacy: remove node arity and allow empty Nexus nodes (Xbars) Wesley W. Terpstra 2017-11-30 14:43:43 -0800
  • 6a25a3b7ac tilelink: we can have helper objects for terminal nodes now too! Wesley W. Terpstra 2017-11-30 11:51:19 -0800
  • 2092cb4ec8 diplomacy: reprotect Node bundles after module construction is completed Wesley W. Terpstra 2017-11-08 15:32:45 -0800
  • fdeed7bbb3 unittest: add an API for describing LazyModule unit tests Wesley W. Terpstra 2017-11-07 16:02:35 -0800
  • cc789e9063 diplomacy: protect more of the unstable API Wesley W. Terpstra 2017-11-07 13:08:30 -0800
  • 8ed9e78903 diplomacy: support cloning of LazyModules Wesley W. Terpstra 2017-11-06 11:30:11 -0800
  • b43bcdfcd1 CloneModule: beat chisel into submission Wesley W. Terpstra 2017-11-07 11:29:49 -0800
  • 1f23f9f865 diplomacy: categorize parameter resolution by direction+side Wesley W. Terpstra 2017-11-02 17:12:20 -0700
  • fbbfc9c096 diplomacy: include edge type in inward/outward node handles Wesley W. Terpstra 2017-11-01 17:03:01 -0700
  • ea03f71f97
         Merge pull request #1135 from freechipsproject/decoupled-loop-fix Wesley W. Terpstra 2017-11-30 18:21:37 -0800
  • 35506279af regmapper: fix d_ready => d_bits loop in RegField.bytes Wesley W. Terpstra 2017-11-30 16:38:45 -0800
  • fc1f5be316 Debug: fix a latent combinational loop (d_ready => d_bits) Wesley W. Terpstra 2017-11-30 16:36:45 -0800
  • a447343074
         Merge pull request #1129 from freechipsproject/add-exception-cover-properties Richard Xia 2017-11-30 16:23:14 -0800
  • 4bd9c477ea Add cover properties for ECALL exceptions. Richard Xia 2017-11-30 11:56:04 -0800
  • 29c70501f2 Add cover properties for exceptions in the core. Richard Xia 2017-11-28 19:49:01 -0800
  • bab0b99d7a
         Merge pull request #1131 from freechipsproject/fix-dcache-tag-ecc-error-under-flush Henry Cook 2017-11-30 12:27:15 -0800
  • 890528c641 Avoid data corruption under correctable tag error during flush Andrew Waterman 2017-11-29 00:31:30 -0800
  • 34d86ef665 Revert "Avoid data corruption under correctable tag error during flush (#1130)" Andrew Waterman 2017-11-29 16:09:30 -0800
  • 44eb4d12b5 Avoid data corruption under correctable tag error during flush (#1130) Andrew Waterman 2017-11-29 09:42:00 -0800
  • 9d489c6dcd
         Merge pull request #1128 from freechipsproject/chisel_527_fixed Megan Wachs 2017-11-27 16:53:02 -0800
  • f554ad7e2c debug: Remove workaround for Chisel 3 #527 Megan Wachs 2017-11-27 10:50:15 -0800
  • 5155eb6059
         Don't emit writeback state machine logic for scratchpad (#1127) Andrew Waterman 2017-11-22 18:40:02 -0600
  • a8d573beeb
         Merge pull request #1123 from freechipsproject/dts-global Wesley W. Terpstra 2017-11-20 19:09:03 -0800
  • 6f3ff634f2 DTS: collect common DTS nodes and move timebase-frequency to cores Wesley W. Terpstra 2017-11-20 18:09:57 -0800
  • 3b299397db diplomacy: bind resources to outer-most binding Wesley W. Terpstra 2017-11-20 17:21:10 -0800
  • 44f99cd9a5 diplomacy: eliminate redundant bindings Wesley W. Terpstra 2017-11-20 17:20:54 -0800
  • baa31edf7d RocketTile: if the dcache is incoherent, report it in DTS Wesley W. Terpstra 2017-11-20 17:19:50 -0800
  • 39f1acfd34
         Merge pull request #1122 from freechipsproject/fix-itim Andrew Waterman 2017-11-20 15:08:25 -0800
  • a60d7d419d icache: add a couple cover points for I$ and ITIM iteraction Yunsup Lee 2017-11-20 13:05:44 -0800
  • 5e94884f09 Fix ITIM deallocation during I$ refill causing data corruption Andrew Waterman 2017-11-20 12:30:40 -0800
  • 66b7a8a5ed Revert "Fix ITIM bug overwriting I$ contents when deallocating ITIM (#1079)" Andrew Waterman 2017-11-20 12:26:04 -0800
  • 342dd82fcf
         Merge pull request #1119 from freechipsproject/verify-blocker-width Wesley W. Terpstra 2017-11-18 15:45:24 -0800
  • ec809483b0 BusBypass: assert fail if the widths of the two slaves do not match Wesley W. Terpstra 2017-11-18 14:36:29 -0800
  • c475c78c2f BusBlocker: don't provide an (incorrect) default value for width Wesley W. Terpstra 2017-11-18 14:33:00 -0800
  • 7a1937242a coreplex: provide correct bus-width for ITIM blockers Wesley W. Terpstra 2017-11-18 14:32:37 -0800
  • 9e0c26f855
         Merge pull request #1118 from freechipsproject/basic-bus-blocker-3 Henry Cook 2017-11-17 21:57:20 -0800
  • 6229c7b1ff
         Merge pull request #1117 from freechipsproject/debug_test_tools Megan Wachs 2017-11-17 20:54:41 -0800
  • f3575404c0 tile: bus blocker needs to know width :( Henry Cook 2017-11-17 20:17:17 -0800
  • b625e68360
         tile: put a BasicBusBlocker inside RocketTile (#1115) Henry Cook 2017-11-17 17:26:48 -0800
  • 68c5981363 debug: bump riscv-tools/riscv-tests/debug for Priv test fixes Megan Wachs 2017-11-17 16:06:50 -0800
  • e7704f46c8
         Add some add'l debug features (#1112) Megan Wachs 2017-11-16 17:14:41 -0800
  • acc8c2bbb3
         Merge pull request #1113 from freechipsproject/bump_spike Gleb Gagarin 2017-11-16 11:19:53 -0800
  • fca2e7f9aa Bumped riscv-tools/riscv-isa-sim Gleb Gagarin 2017-11-15 19:15:47 -0800