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Debug: fix a latent combinational loop (d_ready => d_bits)

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When passed a Wire, WNotify outputs that wire on reads wire => d_bits.
Furthermore, it updates the Wire when a write occures d_ready => wire.

These registers should be returning undefined value on read, anyway.
This commit is contained in:
Wesley W. Terpstra 2017-11-30 16:36:45 -08:00
parent a447343074
commit fc1f5be316
1 changed files with 7 additions and 7 deletions
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14
src/main/scala/devices/debug/Debug.scala
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@ -249,11 +249,11 @@ class DebugCtrlBundle (nComponents: Int)(implicit val p: Parameters) extends Par
*/
// Local reg mapper function : Notify when written, but give the value as well.
object WNotify {
object WNotifyWire {
def apply(n: Int, value: UInt, set: Bool) : RegField = {
RegField(n, value, RegWriteFn((valid, data) => {
RegField(n, UInt(0), RegWriteFn((valid, data) => {
set := valid
when(valid) {value := data}
value := data
Bool(true)
}))
}
@ -881,10 +881,10 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
tlNode.regmap(
// This memory is writable.
HALTED -> Seq(WNotify(sbIdWidth, hartHaltedId, hartHaltedWrEn)),
GOING -> Seq(WNotify(sbIdWidth, hartGoingId, hartGoingWrEn)),
RESUMING -> Seq(WNotify(sbIdWidth, hartResumingId, hartResumingWrEn)),
EXCEPTION -> Seq(WNotify(sbIdWidth, hartExceptionId, hartExceptionWrEn)),
HALTED -> Seq(WNotifyWire(sbIdWidth, hartHaltedId, hartHaltedWrEn)),
GOING -> Seq(WNotifyWire(sbIdWidth, hartGoingId, hartGoingWrEn)),
RESUMING -> Seq(WNotifyWire(sbIdWidth, hartResumingId, hartResumingWrEn)),
EXCEPTION -> Seq(WNotifyWire(sbIdWidth, hartExceptionId, hartExceptionWrEn)),
DATA -> abstractDataMem.map(x => RegField(8, x)),
PROGBUF(cfg)-> programBufferMem.map(x => RegField(8, x)),