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regmapper: fix d_ready => d_bits loop in RegField.bytes 

RegField.bytes updates only those bytes which are written every cycle.
However, there was a bug that it would try to return the updated value on reads.
This led to another TL-spec violating combinational path, just like the Debug module.
This commit is contained in:
Wesley W. Terpstra 2017-11-30 16:38:45 -08:00
parent fc1f5be316
commit 35506279af
1 changed files with 7 additions and 5 deletions
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12
src/main/scala/regmapper/RegField.scala
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@ -113,13 +113,15 @@ object RegField
// than the intended bus width of the device (atomic updates are impossible).
def bytes(reg: UInt, numBytes: Int): Seq[RegField] = {
val pad = reg | UInt(0, width = 8*numBytes)
val bytes = Wire(init = Vec.tabulate(numBytes) { i => pad(8*(i+1)-1, 8*i) })
val oldBytes = Vec.tabulate(numBytes) { i => pad(8*(i+1)-1, 8*i) }
val newBytes = Wire(init = oldBytes)
val valids = Wire(init = Vec.fill(numBytes) { Bool(false) })
when (valids.reduce(_ || _)) { reg := bytes.asUInt }
bytes.zipWithIndex.map { case (b, i) => RegField(8, b,
RegWriteFn((valid, data) => {
when (valids.reduce(_ || _)) { reg := newBytes.asUInt }
Seq.tabulate(numBytes) { i =>
RegField(8, oldBytes(i),
RegWriteFn((valid, data) => {
valids(i) := valid
when (valid) { bytes(i) := data }
when (valid) { newBytes(i) := data }
Bool(true)
}))}}