riscv/rocket-chip
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Merge pull request #1150 from freechipsproject/fix-uncached-unaligned-fetch

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Prevent frontend deadlock fetching from uncacheable memory
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Gleb Gagarin 2017-12-08 11:02:44 -08:00 committed by GitHub
commit 9cc37b8444
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1 changed files with 7 additions and 0 deletions
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7
src/main/scala/rocket/Frontend.scala
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@ -12,6 +12,8 @@ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property._
import chisel3.internal.sourceinfo.SourceInfo
class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) {
val pc = UInt(width = vaddrBitsExtended)
@ -207,6 +209,8 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
// a branch! Flush the BTB and the pipeline.
btb.io.flush := true
fq.io.enq.bits.replay := true
wrong_path := true
ccover(wrong_path, "BTB_NON_CFI_ON_WRONG_PATH", "BTB predicted a non-branch was taken while on the wrong path")
}
when (!prevTaken) {
@ -297,6 +301,9 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
io.errors := icache.io.errors
def alignPC(pc: UInt) = ~(~pc | (coreInstBytes - 1))
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
cover(cond, s"FRONTEND_$label", "Rocket;;" + desc)
}
/** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */