riscv/rocket-chip
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Add cover properties for ECALL exceptions.

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This commit is contained in:
Richard Xia 2017-11-30 11:56:04 -08:00
parent 29c70501f2
commit 4bd9c477ea
1 changed files with 22 additions and 0 deletions
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22
src/main/scala/rocket/CSR.scala
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@ -8,6 +8,7 @@ import Chisel.ImplicitConversions._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property._
import scala.collection.mutable.LinkedHashMap
import Instructions._
@ -532,6 +533,9 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault)
val badaddr_value = Mux(write_badaddr, io.badaddr, 0.U)
val noCause :: mCause :: hCause :: sCause :: uCause :: Nil = Enum(5)
val xcause_dest = Wire(init = noCause)
when (exception) {
when (trapToDebug) {
when (!reg_debug) {
@ -544,6 +548,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
}.elsewhen (delegate) {
reg_sepc := formEPC(epc)
reg_scause := cause
xcause_dest := sCause
reg_sbadaddr := badaddr_value
reg_mstatus.spie := reg_mstatus.sie
reg_mstatus.spp := reg_mstatus.prv
@ -552,6 +557,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
}.otherwise {
reg_mepc := formEPC(epc)
reg_mcause := cause
xcause_dest := mCause
reg_mbadaddr := badaddr_value
reg_mstatus.mpie := reg_mstatus.mie
reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv)
@ -560,6 +566,22 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
}
}
for (
(cover_reg, cover_reg_label) <- List(
(mCause, "MCAUSE"),
(sCause, "SCAUSE")
);
(cover_cause_code, cover_cause_label) <- List(
(Causes.user_ecall, "ECALL_USER"),
(Causes.supervisor_ecall, "ECALL_SUPERVISOR"),
(Causes.hypervisor_ecall, "ECALL_HYPERVISOR"),
(Causes.machine_ecall, "ECALL_MACHINE")
)
) {
cover((xcause_dest === cover_reg) && (cause === UInt(cover_cause_code)),
s"${cover_reg_label}_${cover_cause_label}")
}
when (insn_ret) {
when (Bool(usingVM) && !io.rw.addr(9)) {
reg_mstatus.sie := reg_mstatus.spie