tilelink: we can have helper objects for terminal nodes now too!

The new rule is you should have an object.apply method if you only have a
single .node.

src/main/scala/tilelink/Broadcast.scala

@@ -205,6 +205,12 @@ class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = fa
   }
 }
 
+object TLBroadcast
+{
+  def apply(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = false)(implicit p: Parameters): TLNode =
+    LazyModule(new TLBroadcast(lineBytes, numTrackers, bufferless)).node
+}
+
 class TLBroadcastTracker(id: Int, lineBytes: Int, probeCountBits: Int, bufferless: Boolean, edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Module
 {
   val io = new Bundle {

src/main/scala/tilelink/Fuzzer.scala

@@ -221,6 +221,21 @@ class TLFuzzer(
   }
 }
 
+object TLFuzzer
+{
+  def apply(
+    nOperations: Int,
+    inFlight: Int = 32,
+    noiseMaker: (Int, Bool, Int) => UInt = {
+      (wide: Int, increment: Bool, abs_values: Int) =>
+      LFSRNoiseMaker(wide=wide, increment=increment)
+    },
+    noModify: Boolean = false,
+    overrideAddress: Option[AddressSet] = None,
+    nOrdered: Option[Int] = None)(implicit p: Parameters): TLOutwardNode =
+    LazyModule(new TLFuzzer(nOperations, inFlight, noiseMaker, noModify, overrideAddress, nOrdered)).node
+}
+
 /** Synthesizeable integration test */
 import freechips.rocketchip.unittest._
 

src/main/scala/tilelink/PatternPusher.scala

@@ -84,3 +84,9 @@ class TLPatternPusher(name: String, pattern: Seq[Pattern])(implicit p: Parameter
     tl_out.e.valid := Bool(false)
   }
 }
+
+object TLPatternPusher
+{
+  def apply(name: String, pattern: Seq[Pattern])(implicit p: Parameters): TLOutwardNode =
+    LazyModule(new TLPatternPusher(name, pattern)).node
+}

src/main/scala/tilelink/RAMModel.scala

@@ -333,7 +333,7 @@ class TLRAMModel(log: String = "", ignoreErrorData: Boolean = false)(implicit p:
 
 object TLRAMModel
 {
-  def apply(log: String = "", ignoreErrorData: Boolean = false)(implicit p: Parameters) =
+  def apply(log: String = "", ignoreErrorData: Boolean = false)(implicit p: Parameters): TLNode =
     LazyModule(new TLRAMModel(log, ignoreErrorData)).node
 
   case class MonitorParameters(addressBits: Int, sizeBits: Int)

src/main/scala/tilelink/SRAM.scala

@@ -81,6 +81,18 @@ class TLRAM(
   }
 }
 
+object TLRAM
+{
+  def apply(
+    address: AddressSet,
+    cacheable: Boolean = true,
+    executable: Boolean = true,
+    beatBytes: Int = 4,
+    devName: Option[String] = None,
+    errors: Seq[AddressSet] = Nil)(implicit p: Parameters): TLInwardNode =
+    LazyModule(new TLRAM(address, cacheable, executable, beatBytes, devName, errors)).node
+}
+
 /** Synthesizeable unit testing */
 import freechips.rocketchip.unittest._
 

src/main/scala/tilelink/Xbar.scala

@@ -206,6 +206,9 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parame
 
 object TLXbar
 {
+  def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parameters): TLNode =
+    LazyModule(new TLXbar(policy)).node
+
   def mapInputIds (ports: Seq[TLClientPortParameters ]) = assignRanges(ports.map(_.endSourceId)).map(_.get)
   def mapOutputIds(ports: Seq[TLManagerPortParameters]) = assignRanges(ports.map(_.endSinkId))