riscv
/
rocket-chip
1
0
Fork 0
Code Releases Activity

Merge pull request #1119 from freechipsproject/verify-blocker-width 

Verify blocker width
This commit is contained in:
Wesley W. Terpstra 2017-11-18 15:45:24 -08:00 committed by GitHub
parent 9e0c26f855 ec809483b0
commit 342dd82fcf
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 19 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/coreplex/RocketCoreplex.scala
View File

@ -38,7 +38,7 @@ case class TileSlavePortParams(
(implicit p: Parameters, sourceInfo: SourceInfo): TLInwardNode = {
val tile_slave_blocker =
blockerCtrlAddr
.map(BasicBusBlockerParams(_, coreplex.pbus.beatBytes))
.map(BasicBusBlockerParams(_, coreplex.pbus.beatBytes, coreplex.sbus.beatBytes))
.map(bp => LazyModule(new BasicBusBlocker(bp)))
tile_slave_blocker.foreach { _.controlNode := coreplex.pbus.toVariableWidthSlaves }

2
src/main/scala/devices/tilelink/BusBlocker.scala
View File

@ -115,7 +115,7 @@ class BusBlocker(params: BusBlockerParams)(implicit p: Parameters) extends TLBus
case class BasicBusBlockerParams(
controlAddress: BigInt,
controlBeatBytes: Int,
deviceBeatBytes: Int = 1, // TODO: this is ignored by the BusBypassBar
deviceBeatBytes: Int,
deadlock: Boolean = false)
class BasicBusBlocker(params: BasicBusBlockerParams)(implicit p: Parameters)

31
src/main/scala/devices/tilelink/BusBypass.scala
View File

@ -52,28 +52,31 @@ class TLBusBypassBar(implicit p: Parameters) extends LazyModule
val pending = Bool(OUTPUT)
})
val (in, edge) = node.in(0)
val Seq((out0,_), (out1,_)) = node.out
val (in, edgeIn) = node.in(0)
val Seq((out0, edgeOut0), (out1, edgeOut1)) = node.out
val bce = edge.manager.anySupportAcquireB && edge.client.anySupportProbe
require (edgeOut0.manager.beatBytes == edgeOut1.manager.beatBytes,
s"BusBypass slave device widths mismatch (${edgeOut0.manager.managers.map(_.name)} has ${edgeOut0.manager.beatBytes}B vs ${edgeOut1.manager.managers.map(_.name)} has ${edgeOut1.manager.beatBytes}B)")
val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe
// We need to be locked to the given bypass direction until all transactions stop
val flight = RegInit(UInt(0, width = log2Ceil(3*edge.client.endSourceId+1)))
val flight = RegInit(UInt(0, width = log2Ceil(3*edgeIn.client.endSourceId+1)))
val bypass = RegInit(io.bypass) // synchronous reset required
io.pending := (flight > 0.U)
val (a_first, a_last, _) = edge.firstlast(in.a)
val (b_first, b_last, _) = edge.firstlast(in.b)
val (c_first, c_last, _) = edge.firstlast(in.c)
val (d_first, d_last, _) = edge.firstlast(in.d)
val (e_first, e_last, _) = edge.firstlast(in.e)
val (a_first, a_last, _) = edgeIn.firstlast(in.a)
val (b_first, b_last, _) = edgeIn.firstlast(in.b)
val (c_first, c_last, _) = edgeIn.firstlast(in.c)
val (d_first, d_last, _) = edgeIn.firstlast(in.d)
val (e_first, e_last, _) = edgeIn.firstlast(in.e)
val (a_request, a_response) = (edge.isRequest(in.a.bits), edge.isResponse(in.a.bits))
val (b_request, b_response) = (edge.isRequest(in.b.bits), edge.isResponse(in.b.bits))
val (c_request, c_response) = (edge.isRequest(in.c.bits), edge.isResponse(in.c.bits))
val (d_request, d_response) = (edge.isRequest(in.d.bits), edge.isResponse(in.d.bits))
val (e_request, e_response) = (edge.isRequest(in.e.bits), edge.isResponse(in.e.bits))
val (a_request, a_response) = (edgeIn.isRequest(in.a.bits), edgeIn.isResponse(in.a.bits))
val (b_request, b_response) = (edgeIn.isRequest(in.b.bits), edgeIn.isResponse(in.b.bits))
val (c_request, c_response) = (edgeIn.isRequest(in.c.bits), edgeIn.isResponse(in.c.bits))
val (d_request, d_response) = (edgeIn.isRequest(in.d.bits), edgeIn.isResponse(in.d.bits))
val (e_request, e_response) = (edgeIn.isRequest(in.e.bits), edgeIn.isResponse(in.e.bits))
val a_inc = in.a.fire() && a_first && a_request
val b_inc = in.b.fire() && b_first && b_request