Merge pull request #1119 from freechipsproject/verify-blocker-width
Verify blocker width
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commit
342dd82fcf
@ -38,7 +38,7 @@ case class TileSlavePortParams(
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(implicit p: Parameters, sourceInfo: SourceInfo): TLInwardNode = {
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val tile_slave_blocker =
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blockerCtrlAddr
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.map(BasicBusBlockerParams(_, coreplex.pbus.beatBytes))
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.map(BasicBusBlockerParams(_, coreplex.pbus.beatBytes, coreplex.sbus.beatBytes))
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.map(bp => LazyModule(new BasicBusBlocker(bp)))
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tile_slave_blocker.foreach { _.controlNode := coreplex.pbus.toVariableWidthSlaves }
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@ -115,7 +115,7 @@ class BusBlocker(params: BusBlockerParams)(implicit p: Parameters) extends TLBus
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case class BasicBusBlockerParams(
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controlAddress: BigInt,
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controlBeatBytes: Int,
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deviceBeatBytes: Int = 1, // TODO: this is ignored by the BusBypassBar
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deviceBeatBytes: Int,
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deadlock: Boolean = false)
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class BasicBusBlocker(params: BasicBusBlockerParams)(implicit p: Parameters)
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@ -52,28 +52,31 @@ class TLBusBypassBar(implicit p: Parameters) extends LazyModule
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val pending = Bool(OUTPUT)
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})
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val (in, edge) = node.in(0)
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val Seq((out0,_), (out1,_)) = node.out
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val (in, edgeIn) = node.in(0)
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val Seq((out0, edgeOut0), (out1, edgeOut1)) = node.out
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val bce = edge.manager.anySupportAcquireB && edge.client.anySupportProbe
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require (edgeOut0.manager.beatBytes == edgeOut1.manager.beatBytes,
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s"BusBypass slave device widths mismatch (${edgeOut0.manager.managers.map(_.name)} has ${edgeOut0.manager.beatBytes}B vs ${edgeOut1.manager.managers.map(_.name)} has ${edgeOut1.manager.beatBytes}B)")
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val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe
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// We need to be locked to the given bypass direction until all transactions stop
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val flight = RegInit(UInt(0, width = log2Ceil(3*edge.client.endSourceId+1)))
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val flight = RegInit(UInt(0, width = log2Ceil(3*edgeIn.client.endSourceId+1)))
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val bypass = RegInit(io.bypass) // synchronous reset required
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io.pending := (flight > 0.U)
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val (a_first, a_last, _) = edge.firstlast(in.a)
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val (b_first, b_last, _) = edge.firstlast(in.b)
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val (c_first, c_last, _) = edge.firstlast(in.c)
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val (d_first, d_last, _) = edge.firstlast(in.d)
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val (e_first, e_last, _) = edge.firstlast(in.e)
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val (a_first, a_last, _) = edgeIn.firstlast(in.a)
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val (b_first, b_last, _) = edgeIn.firstlast(in.b)
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val (c_first, c_last, _) = edgeIn.firstlast(in.c)
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val (d_first, d_last, _) = edgeIn.firstlast(in.d)
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val (e_first, e_last, _) = edgeIn.firstlast(in.e)
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val (a_request, a_response) = (edge.isRequest(in.a.bits), edge.isResponse(in.a.bits))
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val (b_request, b_response) = (edge.isRequest(in.b.bits), edge.isResponse(in.b.bits))
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val (c_request, c_response) = (edge.isRequest(in.c.bits), edge.isResponse(in.c.bits))
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val (d_request, d_response) = (edge.isRequest(in.d.bits), edge.isResponse(in.d.bits))
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val (e_request, e_response) = (edge.isRequest(in.e.bits), edge.isResponse(in.e.bits))
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val (a_request, a_response) = (edgeIn.isRequest(in.a.bits), edgeIn.isResponse(in.a.bits))
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val (b_request, b_response) = (edgeIn.isRequest(in.b.bits), edgeIn.isResponse(in.b.bits))
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val (c_request, c_response) = (edgeIn.isRequest(in.c.bits), edgeIn.isResponse(in.c.bits))
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val (d_request, d_response) = (edgeIn.isRequest(in.d.bits), edgeIn.isResponse(in.d.bits))
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val (e_request, e_response) = (edgeIn.isRequest(in.e.bits), edgeIn.isResponse(in.e.bits))
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val a_inc = in.a.fire() && a_first && a_request
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val b_inc = in.b.fire() && b_first && b_request
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