riscv
/
rocket-chip
1
0
Fork 0
Code Releases Activity

groundtest: connect the ibus to a fictitious master (#1140)

This commit is contained in:
Wesley W. Terpstra 2017-12-01 18:28:24 -08:00 committed by GitHub
parent 71ddd797bf
commit dedf396915
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 6 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/main/scala/groundtest/Coreplex.scala
View File

@ -6,6 +6,7 @@ import Chisel._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.coreplex._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.tile._
@ -16,7 +17,8 @@ case object TileId extends Field[Int]
class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
with HasMasterAXI4MemPort
with HasPeripheryTestRAMSlave {
with HasPeripheryTestRAMSlave
with HasInterruptBus {
val tileParams = p(GroundTestTilesKey)
val tiles = tileParams.zipWithIndex.map { case(c, i) => LazyModule(
c.build(i, p.alterPartial {
@ -29,6 +31,9 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
sbus.fromTile(None) { implicit p => TileMasterPortParams(addBuffers = 1).adapt(this)(dc.node) }
}
// No PLIC in ground test; so just sink the interrupts to nowhere
IntSinkNode(IntSinkPortSimple()) := ibus.toPLIC
val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), true, false, pbus.beatBytes))
pbusRAM.node := pbus.toVariableWidthSlaves