riscv/rocket-chip
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  • a44fff5d93 Merge pull request #260 from ucb-bar/w1ToClear Henry Cook 2016-09-08 14:27:03 -0700
  • 60a503dc2f tilelink2 RegField: add a w1ToClear RegField Wesley W. Terpstra 2016-09-08 13:46:56 -0700
  • 99b7e734cd tilelink2 Bundles: fix wrong sink width! Wesley W. Terpstra 2016-09-08 12:14:55 -0700
  • 9bfd8c1cf5 TL2 WidthWidget (#258) Wesley W. Terpstra 2016-09-08 10:38:38 -0700
  • 2c000a99da compartmentalize Top into periphery traits Yunsup Lee 2016-09-08 02:08:57 -0700
  • 8536a2a47d Merge pull request #257 from ucb-bar/fix-non-contiguous-mmio-region-routing Yunsup Lee 2016-09-08 00:03:11 -0700
  • 62e33527d3 Merge branch 'master' into fix-non-contiguous-mmio-region-routing Howard Mao 2016-09-07 23:35:12 -0700
  • 4592558047 Merge pull request #254 from ucb-bar/inferRW Howard Mao 2016-09-07 21:59:05 -0700
  • e35e7b2ee3 Fix routing in non-contiguous MMIO regions Yunsup Lee 2016-09-07 19:28:12 -0700
  • 6be569be9f Turn on the inferRW Firrtl pass Ben Keller 2016-09-07 15:27:26 -0700
  • 7a6f155b2a Merge pull request #253 from ucb-bar/use-companion Howard Mao 2016-09-07 15:07:17 -0700
  • 7603b86239 Merge branch 'master' into use-companion Andrew Waterman 2016-09-07 12:56:55 -0700
  • 58c87bdf32 Merge pull request #245 from ucb-bar/tilelink2.2 Andrew Waterman 2016-09-07 12:56:22 -0700
  • 254f49093c only use companion objects for types Colin Schmidt 2016-09-07 12:32:34 -0700
  • 23d0b31615 Merge branch 'master' into tilelink2.2 Andrew Waterman 2016-09-07 11:47:50 -0700
  • 02a2439222 Support a degenerate PLIC with no interrupts Andrew Waterman 2016-09-07 11:20:21 -0700
  • 92718e4b61 fix null statement in vsli_mem_gen ala firrtl#264 (#252) Colin Schmidt 2016-09-07 11:04:36 -0700
  • 70cfd7ce13 Make DefaultRV32Config be RV32IMAFCS, not RV32IMC Andrew Waterman 2016-09-07 01:58:25 -0700
  • a7f47f3c23 Reduce default BTB size Andrew Waterman 2016-09-07 01:51:27 -0700
  • 9fea4c83da Add RV32F support Andrew Waterman 2016-09-06 23:53:12 -0700
  • 66e9f027e0 Add MuxT to mux on Tuple2 and Tuple3 Andrew Waterman 2016-09-06 23:36:58 -0700
  • 511cc6c5c5 Evaluate arg to Boolean.option lazily Andrew Waterman 2016-09-06 23:36:41 -0700
  • a0dcd42e80 avoid erroneously setting tags valid during flush Andrew Waterman 2016-09-06 17:48:59 -0700
  • fb05f5a07f remove parameter ExtIOAddrMapEntries (#250) Yunsup Lee 2016-09-07 00:05:00 -0700
  • d2421654c4 tilelink2: refactor address into addr_hi on ABC and addr_lo on CD Wesley W. Terpstra 2016-09-06 23:46:44 -0700
  • b76612f357 relax contraint on adding AddrMapEntry to AddrMap (#248) Yunsup Lee 2016-09-06 21:53:55 -0700
  • 7504498dff Merge pull request #247 from ucb-bar/replseqmem_pr Howard Mao 2016-09-06 17:22:18 -0700
  • e95fe646a3 mem_gen failure doesn't create the target Megan Wachs 2016-08-24 12:52:24 -0700
  • bbef3a8d3e Merge pull request #246 from ucb-bar/fix-configstring-printout-problem Howard Mao 2016-09-06 15:31:39 -0700
  • 48098f5e2d Bump FIRRTL to instantiate Sequential Memory Macros Megan Wachs 2016-09-06 14:48:28 -0700
  • 1fec9807f6 allow override of vlsi_mem_gen script Megan Wachs 2016-08-23 17:05:09 -0700
  • aae4230627 tilelink2: fix bugs found by Megan in Legacy converter Wesley W. Terpstra 2016-09-06 13:12:33 -0700
  • 56d81b0034 fix configstring printout with no memory Yunsup Lee 2016-09-06 10:40:11 -0700
  • 54ab14cd9d tilelink2: statically optimize numBeats for simple managers Wesley W. Terpstra 2016-09-05 22:11:03 -0700
  • 314d6ebd6f tilelink2: stricter TransferSizes requirements Wesley W. Terpstra 2016-09-05 22:10:28 -0700
  • 56170c605c tilelink2: be more forgiving in what Legacy TL requires Wesley W. Terpstra 2016-09-05 21:12:51 -0700
  • 3167539331 tilelink2: Narrower must be little-endian Wesley W. Terpstra 2016-09-05 20:42:16 -0700
  • ded246fb95 tilelink2: relax max transfer size; the real requirement is not exceeding alignment Wesley W. Terpstra 2016-09-05 19:45:16 -0700
  • cf0291061d tilelink2: fix a bug in UIntToOH1 triggered if the size was too big Wesley W. Terpstra 2016-09-04 21:54:23 -0700
  • 9f45212c95 tilelink2: Fragmenter needs to update subaddress Wesley W. Terpstra 2016-09-04 20:52:47 -0700
  • 757d46279e tilelink2: expand data correctly in D channel narrower Wesley W. Terpstra 2016-09-04 19:48:21 -0700
  • 0faa8c4051 tilelink2: fix Xbar bug where Mux1H broke FSM if only one manager Wesley W. Terpstra 2016-09-04 18:40:19 -0700
  • a0c25880c7 tilelink2: Monitor should check mask of reconstructed request Wesley W. Terpstra 2016-09-04 18:22:12 -0700
  • df32cc3887 tilelink2: be careful; apply Andrew's masking trick everywhere Wesley W. Terpstra 2016-09-04 17:48:45 -0700
  • fb262558ee tilelink2: helper objects should pass source line from where they were invoked Wesley W. Terpstra 2016-09-04 17:03:10 -0700
  • 1a081b4dd5 tilelink2: Monitor should report which TL connection was the problem Wesley W. Terpstra 2016-09-04 16:54:16 -0700
  • cb54df0a8a tilelink2: tie off unused channels Wesley W. Terpstra 2016-09-04 16:47:18 -0700
  • 68e64a9859 tilelink2: clarify ready-valid use of RegisterRouter Wesley W. Terpstra 2016-09-04 16:17:20 -0700
  • e3b3543841 tilelink2: ensure RegFields don't exceed their bounds Wesley W. Terpstra 2016-09-02 23:01:15 -0700
  • 8343070639 tilelink2: detect 1-bit overflow in register definitions Wesley W. Terpstra 2016-09-02 22:48:00 -0700
  • a1fc01fd6d tilelink2: prevent mapping the same register twice Wesley W. Terpstra 2016-09-02 22:41:42 -0700
  • 81162a2dc9 tilelink2: support attaching a DecoupledIO directly to a register Wesley W. Terpstra 2016-09-02 22:34:51 -0700
  • 6a378e79e3 tilelink2: allow 0-stage backpressure in combinational regmap Wesley W. Terpstra 2016-09-02 21:42:37 -0700
  • 4746cf00ce tilelink2: move files to new uncore directory Wesley W. Terpstra 2016-09-02 20:17:42 -0700
  • e034775bfa tilelink2: use the fancy new hasData functions Wesley W. Terpstra 2016-09-02 20:10:40 -0700
  • 11b0272d91 tilelink2: create optimized hasData method on edges (statically evaluates if known) Wesley W. Terpstra 2016-09-02 19:55:08 -0700
  • 5db7ae262b tilelink2: first version of Narrower (only supports uncached IO) Wesley W. Terpstra 2016-09-02 19:30:07 -0700
  • b004d54d71 tilelink2: add a Fragmenter adapter Wesley W. Terpstra 2016-09-02 15:03:49 -0700
  • ecc3c2a4b2 tilelink2: more efficient one-hot circuits Wesley W. Terpstra 2016-09-02 11:52:47 -0700
  • 3d84795641 tilelink2: use LazyModule(new ...) just like Chisel Module(new ...) Wesley W. Terpstra 2016-09-02 11:13:43 -0700
  • 2069ca5d8d tilelink2: pass sourceInfo using implicits in Monitor Wesley W. Terpstra 2016-09-02 11:12:25 -0700
  • 935b53f3bf tilelink2: explicitly check that fixed fields never change in multibeat Wesley W. Terpstra 2016-09-01 11:34:56 -0700
  • e652cd155b tilelink2: edge parameters on the same link had better match Wesley W. Terpstra 2016-09-01 11:13:36 -0700
  • c411a3e77f tilelink2: simpler sizes requirement for users to understand Wesley W. Terpstra 2016-09-01 11:12:59 -0700
  • ab998c08f1 tilelink2: save some hardware in HintHandler if no BCE Wesley W. Terpstra 2016-08-31 17:44:48 -0700
  • 18e7d4cd65 tilelink2: make it possible to write Node-only adapters Wesley W. Terpstra 2016-08-31 16:45:18 -0700
  • 4a401fc480 tilelink2: add a Buffer adapter to insert pipeline stages Wesley W. Terpstra 2016-08-31 15:53:25 -0700
  • 50f0dee69e tilelink2: add an IdentityNode for adapters that change nothing Wesley W. Terpstra 2016-08-31 15:47:07 -0700
  • 9cd2991fb3 tilelink2: AddressSet always has an assigned base address Wesley W. Terpstra 2016-08-31 14:49:18 -0700
  • ae2bc4da21 tilelink2: refactor RegField into interface and implementation Wesley W. Terpstra 2016-08-31 13:37:20 -0700
  • d6727abbbc tilelink2: rename Operations to Edges (as it only includes Edges) Wesley W. Terpstra 2016-08-31 13:30:46 -0700
  • ee3e31cb23 tilelink2: refactor TLNodes into a seperate file Wesley W. Terpstra 2016-08-31 13:30:06 -0700
  • 69b3de92a8 tilelink2: decouple BaseNode from TileLink bus (so it can be reused) Wesley W. Terpstra 2016-08-31 12:17:55 -0700
  • c785375276 tilelink2: use 'connect' instead of TL-specific 'tl' to connect nodes Wesley W. Terpstra 2016-08-31 10:43:34 -0700
  • 05221d7073 tilelink2: rename Bases.scala to LazyModule.scala Wesley W. Terpstra 2016-08-31 10:38:00 -0700
  • 8d54ae8508 tilelink2: move TL-specific stuff out of the LazyModule base classes Wesley W. Terpstra 2016-08-31 10:37:30 -0700
  • f99a3dbec7 tilelink2: rename Factory=>LazyModule and TLModule=>LazyModuleImp Wesley W. Terpstra 2016-08-31 10:25:46 -0700
  • 5b31fb81fe tilelink2: IDNode needs to be specialized for output vs. input passthrough Wesley W. Terpstra 2016-08-30 19:26:01 -0700
  • eac4d44131 tilelink2: don't apply HintHandler to B=>C by default Wesley W. Terpstra 2016-08-30 16:16:45 -0700
  • cc8112d02e tilelink2: pass E through the HintHandler Wesley W. Terpstra 2016-08-30 16:10:42 -0700
  • a72f7115ae tilelink2: optimize support testing circuits Wesley W. Terpstra 2016-08-30 16:02:46 -0700
  • f0cfd81820 tilelink2: add an adapter to add support for Hints to devices Wesley W. Terpstra 2016-08-30 15:52:04 -0700
  • 5f6ca0bd0d tilelink2: rename wmask => mask since it also applies to reads Wesley W. Terpstra 2016-08-30 15:06:37 -0700
  • 7347b0c4dd tilelink2: TLLegacy converts from legacy TileLink to TileLink2 Wesley W. Terpstra 2016-08-30 15:01:49 -0700
  • fa472e38fb tilelink2: monitor error line legality Wesley W. Terpstra 2016-08-30 14:54:13 -0700
  • edb17d1e34 tilelink2: document allowed (and required) response messages Wesley W. Terpstra 2016-08-30 14:43:07 -0700
  • ec1f901a38 tilelink2: move error from type into Bundle and add HintAck Wesley W. Terpstra 2016-08-30 14:38:26 -0700
  • 534d7f6eb6 tilelink2: implement SRAM manager Wesley W. Terpstra 2016-08-30 11:46:05 -0700
  • 32894a8e20 tilelink2: transfers must never exceed 4kB Wesley W. Terpstra 2016-08-30 10:40:35 -0700
  • dd27a60daa tilelink2: use consistent in/out ports for TLSimpleFactories Wesley W. Terpstra 2016-08-30 10:40:54 -0700
  • 1a87eef3e2 tilelink2: add atomic message types Wesley W. Terpstra 2016-08-30 10:40:14 -0700
  • 5f7711a0c0 tilelink2: add an intermediate type for simple factories Wesley W. Terpstra 2016-08-29 17:53:31 -0700
  • 967d8f108c tilelink2: support ready-valid enqueue+dequeue on register fields Wesley W. Terpstra 2016-08-29 15:33:10 -0700
  • 77cf186cf0 tilelink2: make bundle parameterization reusable Wesley W. Terpstra 2016-08-29 17:02:04 -0700
  • 594850eaae tilelink2: assert-fail on something more user understandable Wesley W. Terpstra 2016-08-29 12:44:11 -0700
  • dc1164a996 tilelink2: defer bundle construction until after Module base class instantiated Wesley W. Terpstra 2016-08-29 11:08:37 -0700
  • 18e149098a tilelink2: connect abstract register-based modules to TileLink Wesley W. Terpstra 2016-08-26 15:48:48 -0700
  • 917a9c8e5d tilelink2: forward declarations for message constructors Wesley W. Terpstra 2016-08-26 15:32:20 -0700
  • 4649c42f50 tilelink2: use a new type in the signature of null-parameter Bundle methods Wesley W. Terpstra 2016-08-26 15:03:39 -0700
  • 0ff33a31a4 tilelink2: add a stub SRAM manager Wesley W. Terpstra 2016-08-26 14:16:17 -0700