riscv/rocket-chip
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  • 8710fe9561 Add WithClockFrequency class to update frequencies ml507 klemens 2018-06-06 01:04:38 +02:00
  • 81d631a6a1 Add small rocket config with fpu and mmu klemens 2018-05-19 18:56:56 +02:00
  • 6df42fc360 ml507: readmemh does not support dynamic paths on ISE klemens 2018-05-01 00:10:15 +02:00
  • 4ba8acb4aa TLRAM: add support for ECC (#1304) Wesley W. Terpstra 2018-03-22 14:27:43 -07:00
  • 12583af4a8 buswrapper: remove buffer chains from api (#1303) Henry Cook 2018-03-21 23:44:05 -07:00
  • 4cfae27efd Implement Hauser misa.C misalignment proposal (#1301) Andrew Waterman 2018-03-21 23:42:01 -07:00
  • 7f96da2288 ECC: support poison during encode (#1166) Wesley W. Terpstra 2018-03-21 16:29:24 -07:00
  • 7593baf2aa Merge pull request #1299 from freechipsproject/serializable-metadata Henry Cook 2018-03-21 11:58:05 -07:00
  • f48c2767d7 subsytem: change front bus buffer defaults (#1300) Henry Cook 2018-03-21 11:56:22 -07:00
  • 894960678c Update Debug Module registers (#1296) Megan Wachs 2018-03-20 14:01:22 -07:00
  • 70895b6ffa rocket: make RocketTileParams trivial to serialize Henry Cook 2018-03-19 12:28:48 -07:00
  • 12997a644d tilelink: TLToAXI4IdMapEntry Henry Cook 2018-03-15 12:33:34 -07:00
  • 3cb9e57b5e diplomacy: AddressMapEntry and BindingScope.collect Henry Cook 2018-03-14 22:46:36 -07:00
  • 2489a08328 Header required for -DVM_TRACE=1 (#1294) Edmond Cote 2018-03-19 18:07:28 -07:00
  • 9a56e44e32 Fix typo in RAMModel Get printf (#1293) John Wright 2018-03-19 11:30:41 -07:00
  • d6bc9c53f0 Save a little power during reset by not writing D$ tags (#1287) Andrew Waterman 2018-03-15 19:23:09 -05:00
  • 78dad3e89b Merge pull request #1279 from freechipsproject/ipxact_descs Megan Wachs 2018-03-14 06:46:00 -07:00
  • 4e11491531 Merge remote-tracking branch 'origin/master' into ipxact_descs Megan Wachs 2018-03-13 09:26:47 -07:00
  • 1c1b6e8ffe Merge pull request #1282 from freechipsproject/revert_debug_flags Megan Wachs 2018-03-13 09:09:39 -07:00
  • d00a0bba32 Revert "Debug: don't need to fully populate flags array" Megan Wachs 2018-03-12 21:29:55 -07:00
  • 59d5e61366 regmapper: refactor how json is emitted Henry Cook 2018-03-11 18:06:35 -07:00
  • ea89259dd4 RegFieldDesc: reserved omits () Henry Cook 2018-03-11 12:12:40 -07:00
  • 15e058e3da RegFieldDesc: change how reserved is indicated Megan Wachs 2018-03-09 17:38:23 -08:00
  • d889a0ca16 RegFieldDesc: add volatile to cause reg in BUE Megan Wachs 2018-03-09 17:20:38 -08:00
  • e0c3c63826 RegFieldDesc: Update the .bytes method to emit reserved register fields instead of applying the same description to the registers that it doesn't actually do anything with (the padding registers) Megan Wachs 2018-03-09 15:10:43 -08:00
  • 0fcacd37df RegFieldDesc: mark some more registers as volatile Megan Wachs 2018-03-09 15:10:43 -08:00
  • 7458378a4a RegFieldDesc: Update reg field descs to be more correct for devices. Megan Wachs 2018-03-09 12:22:28 -08:00
  • 3063fd1b46 RegFieldDesc: update DescribedReg to suppot new features Megan Wachs 2018-03-09 11:47:03 -08:00
  • 2f239f2a9a RegFieldDesc: Add more features to support more IP-XACT like descriptions & emit them in the JSON Megan Wachs 2018-03-09 11:29:17 -08:00
  • e07b37c7ad Merge pull request #1186 from edcote/patch-1 Henry Cook 2018-03-11 11:40:25 -07:00
  • d3c16258fd Merge pull request #1280 from freechipsproject/reg-desc-anno Henry Cook 2018-03-10 19:50:54 -08:00
  • 0e0963d360 util: use chisel3.core.dontTouch Henry Cook 2018-03-10 17:04:46 -08:00
  • 99862942fe Merge pull request #1276 from freechipsproject/reg-desc-anno Henry Cook 2018-03-08 19:04:23 -08:00
  • 1b93b27da4 util: restore dontTouch annotation; Chisel's is broken on 0 element Aggregates Henry Cook 2018-03-08 16:12:15 -08:00
  • 933f2ce958 Bump riscv-tools for riscv-fesvr submodule ptr fix (#1275) Schuyler Eldridge 2018-03-08 17:27:51 -05:00
  • d6e2c1a73f more != wire deprecations Henry Cook 2018-03-08 12:36:51 -08:00
  • 32592377c6 sbt: bump json4s-jackson to 3.5.3 Henry Cook 2018-03-08 12:31:52 -08:00
  • 8bb397a1b9 Fix VCS argument parsing (#1266) Schuyler Eldridge 2018-03-08 01:59:04 -05:00
  • 7d146f3401 Merge pull request #1273 from freechipsproject/no_jtag_vpi Megan Wachs 2018-03-07 14:50:26 -08:00
  • ef7a6115b7 vsim: don't need VPI without JTAGVPI Megan Wachs 2018-03-07 10:58:09 -08:00
  • 15dc7f6760 JTAGVPI: remove it from Chisel as it is unused Megan Wachs 2018-03-07 10:55:45 -08:00
  • 42e614550c JTAGVPI: remove it in favor of remote bitbang Megan Wachs 2018-03-07 10:53:49 -08:00
  • 64b707cbb6 Bump Chisel and FIRRTL for annotations refactor (#1261) Jack Koenig 2018-03-07 13:22:38 -05:00
  • d0b46c5b8f Align RoCCIO with new cloneType (#1270) Schuyler Eldridge 2018-03-06 20:53:51 -05:00
  • f1bd9c99aa Merge pull request #1262 from freechipsproject/beu-regfield Megan Wachs 2018-03-06 12:31:00 -08:00
  • f00e9576e3 Merge pull request #1263 from freechipsproject/sim_jtag_reset Megan Wachs 2018-03-06 11:28:51 -08:00
  • b669fb3d6a Merge remote-tracking branch 'origin/master' into beu-regfield Megan Wachs 2018-03-06 11:04:17 -08:00
  • 2a0e67ab15 Merge pull request #1267 from freechipsproject/plic_source_0 Megan Wachs 2018-03-06 11:03:26 -08:00
  • a3d99e5ba2 DescribedReg: fix some imports Megan Wachs 2018-03-06 11:02:10 -08:00
  • a20998e215 SimJTAG: fix verilog typo Megan Wachs 2018-03-05 16:27:17 -08:00
  • 8856953905 DescribedReg: move to regmapper Megan Wachs 2018-03-05 16:12:14 -08:00
  • 4256d99a9b PLIC: priority/threshold are really WARL (RWSPECIAL). Explain why. Megan Wachs 2018-03-05 16:10:05 -08:00
  • 41d1a62713 PLIC: Update RegFieldDesc to reflect the fact that source 0 isn't like all the others Megan Wachs 2018-03-05 15:29:14 -08:00
  • bd3a72e585 Merge remote-tracking branch 'origin/master' into sim_jtag_reset Megan Wachs 2018-03-05 12:41:39 -08:00
  • e3be5db3e6 BUE: more verbose register descriptions Megan Wachs 2018-03-05 11:21:10 -08:00
  • 878a357a0d RegFieldDesc: Add utilities for generating and describing registers at the same time. Megan Wachs 2018-03-05 11:22:24 -08:00
  • 5eae81038d SimJTAG: make the reset/init connectivity more flexible. This is because you may want to seperate the two Megan Wachs 2018-03-02 17:29:17 -08:00
  • 644ba6dafa Add BusErrorUnit RegFieldDesc Andrew Waterman 2018-03-02 17:25:13 -08:00
  • 8c6e745653 Bump chisel and firrtl (#1232) Jack Koenig 2018-03-01 15:19:12 -08:00
  • 20a8876856 Merge pull request #1190 from freechipsproject/bus-api Henry Cook 2018-03-01 01:13:50 -08:00
  • cdd2a9227f Merge pull request #1256 from freechipsproject/json_emit_enums Megan Wachs 2018-02-28 11:32:14 -08:00
  • d13dc8ac2a RegFieldDesc: Emit enumerations if they exist Megan Wachs 2018-02-28 09:42:25 -08:00
  • a48dd575b2 Merge pull request #1254 from freechipsproject/amo-aqrl Andrew Waterman 2018-02-27 19:49:40 -06:00
  • 86c10b3cef Merge pull request #1250 from seldridge/add-jtag-vpi-c-vsim Henry Cook 2018-02-26 15:40:12 -07:00
  • 4bcc42550e Remove JTAG vpi from VCS build Schuyler Eldridge 2018-02-26 15:12:18 -05:00
  • 47d63d6baa Merge pull request #1251 from freechipsproject/rocket_covers bipult 2018-02-25 09:01:33 -08:00
  • eb6e192ec0 Fix mapping of acquire/release AMOs to fence operations Andrew Waterman 2018-02-23 16:39:47 -08:00
  • 30c0635bb3 subsystem: add some inter-wrapper buffer params Henry Cook 2018-02-23 14:50:39 -08:00
  • 95294bbdcb PatternPusher: put data at correct address when misaligned (#1249) Wesley W. Terpstra 2018-02-23 15:20:56 -08:00
  • d0e350976a Add jtag_vpi.c to sources for vsim Schuyler Eldridge 2018-02-23 15:32:10 -05:00
  • ad823ef43c subsystem: pbus crossing type Henry Cook 2018-02-23 13:51:31 -08:00
  • 5725e17969 subsystem: even more general coupler methods Henry Cook 2018-02-23 12:50:51 -08:00
  • 87eed645d8 Fix JTAG cover description (#1248) Jacob Chang 2018-02-23 12:13:31 -08:00
  • 5b1d72c776 subsystem: expose HasTiles Parameters Henry Cook 2018-02-22 23:46:08 -08:00
  • 099bbec666 subsystem: more buswrapper coupling methods Henry Cook 2018-02-22 23:45:21 -08:00
  • 2e548c9ad2 Added functional covers Bipul Talukdar 2018-02-22 23:20:12 -08:00
  • 69b48b623a Merge pull request #1247 from freechipsproject/misa-c Andrew Waterman 2018-02-22 22:53:49 -08:00
  • aad75f2285 Implement misa.C proposal Andrew Waterman 2018-02-22 15:12:19 -08:00
  • c1ee31d133 Fix debug trigger point for stores Andrew Waterman 2018-02-22 14:56:57 -08:00
  • 78883d13e8 subsystem: add TLIdentity.gen and make wrappers more flexible Henry Cook 2018-02-21 18:22:06 -08:00
  • eaa908d44f subsystem: more buswrapper methods Henry Cook 2018-02-21 14:40:26 -08:00
  • e237f72539 subsystem: XSubsystemModule => XSubsystemModuleImp Henry Cook 2018-02-21 12:51:16 -08:00
  • 1af02f754e groundtest: fix filename Henry Cook 2018-02-21 12:46:55 -08:00
  • 030c6f0206 subsystem: bus wrappers now in BaseSubsystem Henry Cook 2018-02-20 17:10:16 -08:00
  • b617e26c13 util: augment String and use to name couplers Henry Cook 2018-02-20 17:09:30 -08:00
  • a6d3965491 tilelink: bus wrapper scopes called 'couplers' Henry Cook 2018-02-16 18:03:40 -08:00
  • 57edd7facf subsystem: streamline toTile and fromTile attachment Henry Cook 2018-02-16 15:58:55 -08:00
  • ef3addee7b diplomacy: put full module + instance path into graphml Description Wesley W. Terpstra 2017-12-01 14:11:41 -08:00
  • 62aee56807 diplomacy: base instance names on ValName and module names on className Henry Cook 2018-02-16 13:58:33 -08:00
  • 3f436a7612 subsystem: new bus attachment api Henry Cook 2018-02-15 14:01:49 -08:00
  • 8462ea3d5b coreplex => subsystem Henry Cook 2018-01-12 12:29:27 -08:00
  • 32c5c3c04d Merge pull request #1245 from freechipsproject/rv32d Andrew Waterman 2018-02-21 11:05:44 -08:00
  • 8998a97ea1 Preserve WithRV32 behavior: FLEN = 32 Andrew Waterman 2018-02-20 18:28:47 -08:00
  • 1dc1e2c099 support testing RV32D configs Andrew Waterman 2018-02-20 15:45:07 -08:00
  • d4fb7ad6a2 DefaultRV32Config should provide fdiv/fsqrt Andrew Waterman 2018-02-20 15:44:30 -08:00
  • b487448961 Add FPUParams.fLen option, decoupled from xLen Andrew Waterman 2018-02-20 15:43:49 -08:00
  • 5e35015651 Minor Rocket fixes to support fLen != xLen Andrew Waterman 2018-02-20 15:42:50 -08:00
  • bd29184e11 debug: get beatBytes from pbus, not XLen Andrew Waterman 2018-02-20 15:37:36 -08:00
  • 62f9b84439 plic: get beatBytes from pbus, not XLen Andrew Waterman 2018-02-20 15:37:23 -08:00
  • 52e22a1dd8 clint: get beatBytes from pbus, not XLen Andrew Waterman 2018-02-20 15:36:57 -08:00