Merge pull request #1276 from freechipsproject/reg-desc-anno

sbt: bump json4s-jackson to 3.5.3

build.sbt

@@ -15,7 +15,7 @@ lazy val commonSettings = Seq(
   traceLevel   := 15,
   scalacOptions ++= Seq("-deprecation","-unchecked"),
   libraryDependencies ++= Seq("org.scala-lang" % "scala-reflect" % scalaVersion.value),
-  libraryDependencies ++= Seq("org.json4s" %% "json4s-jackson" % "3.5.0"),
+  libraryDependencies ++= Seq("org.json4s" %% "json4s-jackson" % "3.5.3"),
   addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full)
 )
 

src/main/scala/devices/debug/DebugTransport.scala

@@ -172,7 +172,7 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
   // But there is actually no case in the current design where you SHOULD get an error,
   // as we haven't implemented Bus Masters or Serial Ports, which are the only cases errors
   // can occur.
-  nonzeroResp := stickyNonzeroRespReg | (io.dmi.resp.valid & (io.dmi.resp.bits.resp != UInt(0)))
+  nonzeroResp := stickyNonzeroRespReg | (io.dmi.resp.valid & (io.dmi.resp.bits.resp =/= UInt(0)))
   assert(!nonzeroResp, "There is no reason to get a non zero response in the current system.");
   assert(!stickyNonzeroRespReg, "There is no reason to have a sticky non zero response in the current system.");
 

src/main/scala/devices/tilelink/BusBypass.scala

@@ -103,7 +103,7 @@ class TLBusBypassBar(implicit p: Parameters) extends LazyModule
     flight := next_flight
 
     when (next_flight === UInt(0)) { bypass := io.bypass }
-    val stall = (bypass != io.bypass) && a_first
+    val stall = (bypass =/= io.bypass) && a_first
 
     out0.a.valid := !stall && in.a.valid &&  bypass
     out1.a.valid := !stall && in.a.valid && !bypass

src/main/scala/util/Misc.scala

@@ -4,7 +4,7 @@
 package freechips.rocketchip.util
 
 import Chisel._
-import chisel3.experimental.{dontTouch, RawModule}
+import chisel3.experimental.{ChiselAnnotation, RawModule}
 import freechips.rocketchip.config.Parameters
 import scala.math._
 
@@ -14,6 +14,13 @@ class ParameterizedBundle(implicit p: Parameters) extends Bundle
 trait DontTouch {
   self: RawModule =>
 
+  def dontTouch(data: Data): Unit = data match {
+     case agg: Aggregate =>
+       agg.getElements.foreach(dontTouch)
+     case elt: Element =>
+       annotate(ChiselAnnotation(elt, classOf[firrtl.Transform], "DONTtouch!"))
+  }
+
   /** Marks every port as don't touch
     *
     * @note This method can only be called after the Module has been fully constructed