more != wire deprecations
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@ -172,7 +172,7 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
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// But there is actually no case in the current design where you SHOULD get an error,
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// as we haven't implemented Bus Masters or Serial Ports, which are the only cases errors
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// can occur.
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nonzeroResp := stickyNonzeroRespReg | (io.dmi.resp.valid & (io.dmi.resp.bits.resp != UInt(0)))
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nonzeroResp := stickyNonzeroRespReg | (io.dmi.resp.valid & (io.dmi.resp.bits.resp =/= UInt(0)))
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assert(!nonzeroResp, "There is no reason to get a non zero response in the current system.");
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assert(!stickyNonzeroRespReg, "There is no reason to have a sticky non zero response in the current system.");
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@ -103,7 +103,7 @@ class TLBusBypassBar(implicit p: Parameters) extends LazyModule
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flight := next_flight
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when (next_flight === UInt(0)) { bypass := io.bypass }
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val stall = (bypass != io.bypass) && a_first
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val stall = (bypass =/= io.bypass) && a_first
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out0.a.valid := !stall && in.a.valid && bypass
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out1.a.valid := !stall && in.a.valid && !bypass
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