subsystem: XSubsystemModule => XSubsystemModuleImp

src/main/scala/groundtest/GroundTestSubsystem.scala

@@ -33,10 +33,10 @@ class GroundTestSubsystem(implicit p: Parameters) extends BaseSubsystem
   // No PLIC in ground test; so just sink the interrupts to nowhere
   IntSinkNode(IntSinkPortSimple()) := ibus.toPLIC
 
-  override lazy val module = new GroundTestSubsystemModule(this)
+  override lazy val module = new GroundTestSubsystemModuleImp(this)
 }
 
-class GroundTestSubsystemModule[+L <: GroundTestSubsystem](_outer: L) extends BaseSubsystemModule(_outer)
+class GroundTestSubsystemModuleImp[+L <: GroundTestSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
     with HasMasterAXI4MemPortModuleImp {
   val success = IO(Bool(OUTPUT))
 

src/main/scala/subsystem/BaseSubsystem.scala

@@ -16,7 +16,7 @@ abstract class BareSubsystem(implicit p: Parameters) extends LazyModule with Bin
   lazy val json = JSON(bindingTree)
 }
 
-abstract class BareSubsystemModule[+L <: BareSubsystem](_outer: L) extends LazyModuleImp(_outer) {
+abstract class BareSubsystemModuleImp[+L <: BareSubsystem](_outer: L) extends LazyModuleImp(_outer) {
   val outer = _outer
   ElaborationArtefacts.add("graphml", outer.graphML)
   ElaborationArtefacts.add("dts", outer.dts)
@@ -27,7 +27,7 @@ abstract class BareSubsystemModule[+L <: BareSubsystem](_outer: L) extends LazyM
 
 /** Base Subsystem class with no peripheral devices or ports added */
 abstract class BaseSubsystem(implicit p: Parameters) extends BareSubsystem {
-  override val module: BaseSubsystemModule[BaseSubsystem]
+  override val module: BaseSubsystemModuleImp[BaseSubsystem]
 
   // These are wrappers around the standard buses available in all subsytems, where
   // peripherals, tiles, ports, and other masters and slaves can attach themselves.
@@ -97,7 +97,7 @@ abstract class BaseSubsystem(implicit p: Parameters) extends BareSubsystem {
   }
 }
 
-abstract class BaseSubsystemModule[+L <: BaseSubsystem](_outer: L) extends BareSubsystemModule(_outer) {
+abstract class BaseSubsystemModuleImp[+L <: BaseSubsystem](_outer: L) extends BareSubsystemModuleImp(_outer) {
   println("Generated Address Map")
   private val aw = (outer.sbus.busView.bundle.addressBits-1)/4 + 1
   private val fmt = s"\t%${aw}x - %${aw}x %c%c%c%c%c %s"

src/main/scala/subsystem/RocketSubsystem.scala

@@ -148,10 +148,10 @@ trait HasRocketTilesModuleImp extends HasTilesModuleImp
 class RocketSubsystem(implicit p: Parameters) extends BaseSubsystem
     with HasRocketTiles {
   val tiles = rocketTiles
-  override lazy val module = new RocketSubsystemModule(this)
+  override lazy val module = new RocketSubsystemModuleImp(this)
 }
 
-class RocketSubsystemModule[+L <: RocketSubsystem](_outer: L) extends BaseSubsystemModule(_outer)
+class RocketSubsystemModuleImp[+L <: RocketSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
     with HasRocketTilesModuleImp {
   tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) =>
     wire.clock := clock

src/main/scala/system/ExampleRocketSystem.scala

@@ -16,10 +16,10 @@ class ExampleRocketSystem(implicit p: Parameters) extends RocketSubsystem
     with HasSlaveAXI4Port
     with HasPeripheryBootROM
     with HasSystemErrorSlave {
-  override lazy val module = new ExampleRocketSystemModule(this)
+  override lazy val module = new ExampleRocketSystemModuleImp(this)
 }
 
-class ExampleRocketSystemModule[+L <: ExampleRocketSystem](_outer: L) extends RocketSubsystemModule(_outer)
+class ExampleRocketSystemModuleImp[+L <: ExampleRocketSystem](_outer: L) extends RocketSubsystemModuleImp(_outer)
     with HasRTCModuleImp
     with HasExtInterruptsModuleImp
     with HasMasterAXI4MemPortModuleImp