TLRAM: add support for ECC (#1304)
This commit is contained in:
Wesley W. Terpstra
GitHub
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12583af4a8
commit
4ba8acb4aa
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@ -22,10 +22,9 @@ abstract class DiplomaticSRAM(
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def mask: List[Boolean] = bigBits(address.mask >> log2Ceil(beatBytes))
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// Use single-ported memory with byte-write enable
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def makeSinglePortedByteWriteSeqMem(size: Int) = {
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def makeSinglePortedByteWriteSeqMem(size: Int, lanes: Int = beatBytes, bits: Int = 8) = {
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// We require the address range to include an entire beat (for the write mask)
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require ((address.mask & (beatBytes-1)) == beatBytes-1)
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val mem = SeqMem(size, Vec(beatBytes, Bits(width = 8)))
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val mem = SeqMem(size, Vec(lanes, Bits(width = bits)))
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devName.foreach(n => mem.suggestName(n.split("-").last))
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mem
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}
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@ -13,10 +13,16 @@ class TLRAM(
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cacheable: Boolean = true,
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executable: Boolean = true,
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beatBytes: Int = 4,
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eccBytes: Int = 1,
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devName: Option[String] = None,
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errors: Seq[AddressSet] = Nil)
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errors: Seq[AddressSet] = Nil,
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code: Code = new IdentityCode)
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(implicit p: Parameters) extends DiplomaticSRAM(address, beatBytes, devName)
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{
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require (eccBytes >= 1 && isPow2(eccBytes))
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require (beatBytes >= 1 && isPow2(beatBytes))
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require (eccBytes <= beatBytes, s"TLRAM eccBytes (${eccBytes}) > beatBytes (${beatBytes}). Use a WidthWidget=>Fragmenter=>SRAM if you need high density and narrow ECC; it will do bursts efficiently")
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val node = TLManagerNode(Seq(TLManagerPortParameters(
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Seq(TLManagerParameters(
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address = List(address) ++ errors,
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@ -33,46 +39,127 @@ class TLRAM(
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lazy val module = new LazyModuleImp(this) {
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val (in, edge) = node.in(0)
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val width = code.width(eccBytes*8)
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val lanes = beatBytes/eccBytes
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val addrBits = (mask zip edge.addr_hi(in.a.bits).toBools).filter(_._1).map(_._2)
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val a_legal = address.contains(in.a.bits.address)
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val memAddress = Cat(addrBits.reverse)
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val mem = makeSinglePortedByteWriteSeqMem(1 << addrBits.size)
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val mem = makeSinglePortedByteWriteSeqMem(1 << addrBits.size, lanes, width)
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val d_full = RegInit(Bool(false))
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val d_read = Reg(Bool())
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val d_size = Reg(UInt())
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val d_source = Reg(UInt())
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val d_data = Wire(UInt())
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val d_legal = Reg(Bool())
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/* This block uses a two-stage pipeline; A=>D
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* Both stages vie for access to the single SRAM port.
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* Stage D has absolute priority over stage A.
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* - read-modify-writeback for sub-lane access happens here
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* - writeback of correctable data happens here
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* - both actions may occur concurrently
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* Stage A has lower priority and will stall if blocked
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* - read operations happen here
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* - full-lane write operations happen here
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*/
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// Flow control
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when (in.d.fire()) { d_full := Bool(false) }
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when (in.a.fire()) { d_full := Bool(true) }
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in.d.valid := d_full
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in.a.ready := in.d.ready || !d_full
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// D stage registers from A
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val d_full = RegInit(Bool(false))
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val d_ram_valid = RegInit(Bool(false)) // true if we just read-out from SRAM
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val d_size = Reg(UInt())
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val d_source = Reg(UInt())
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val d_legal = Reg(Bool())
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val d_read = Reg(Bool())
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val d_address = Reg(UInt(width = addrBits.size))
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val d_rmw_mask = Reg(UInt(width = beatBytes))
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val d_rmw_data = Reg(UInt(width = 8*beatBytes))
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// Decode raw unregistered SRAM output
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val d_raw_data = Wire(Vec(lanes, Bits(width = width)))
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val d_decoded = d_raw_data.map(lane => code.decode(lane))
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val d_corrected = Cat(d_decoded.map(_.corrected).reverse)
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val d_uncorrected = Cat(d_decoded.map(_.uncorrected).reverse)
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val d_correctable = d_decoded.map(_.correctable)
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val d_uncorrectable = d_decoded.map(_.uncorrectable)
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val d_need_fix = d_correctable.reduce(_ || _)
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val d_error = d_uncorrectable.reduce(_ || _)
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// What does D-stage want to write-back?
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val d_wb_data = Vec(Seq.tabulate(beatBytes) { i =>
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val upd = d_rmw_mask(i)
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val rmw = d_rmw_data (8*(i+1)-1, 8*i)
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val fix = d_corrected(8*(i+1)-1, 8*i) // safe to use, because D-stage write-back always wins arbitration
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Mux(upd, rmw, fix)
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}.grouped(eccBytes).map(lane => Cat(lane.reverse)).toList)
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val (d_wb_lanes, d_wb_poison) = Seq.tabulate(lanes) { i =>
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val upd = d_rmw_mask(eccBytes*(i+1)-1, eccBytes*i)
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(upd.orR || d_correctable(i),
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!upd.andR && d_uncorrectable(i)) // sub-lane writes should not correct uncorrectable
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}.unzip
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val d_wb = d_rmw_mask.orR || (d_ram_valid && d_need_fix)
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// Extend the validity of SRAM read-out
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val d_held_data = RegEnable(d_corrected, d_ram_valid)
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val d_held_error = RegEnable(d_error, d_ram_valid)
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in.d.bits := edge.AccessAck(d_source, d_size, !d_legal)
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// avoid data-bus Mux
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in.d.bits.data := d_data
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in.d.bits.opcode := Mux(d_read, TLMessages.AccessAckData, TLMessages.AccessAck)
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in.d.bits.param := UInt(0)
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in.d.bits.size := d_size
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in.d.bits.source := d_source
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in.d.bits.sink := UInt(0)
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// It is safe to use uncorrected data here because of d_pause
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in.d.bits.data := Mux(d_ram_valid, d_uncorrected, d_held_data)
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in.d.bits.error := !d_legal || Mux(d_ram_valid, d_error, d_held_error)
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val read = in.a.bits.opcode === TLMessages.Get
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val rdata = Wire(Vec(beatBytes, Bits(width = 8)))
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val wdata = Vec.tabulate(beatBytes) { i => in.a.bits.data(8*(i+1)-1, 8*i) }
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d_data := Cat(rdata.reverse)
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// Formulate a response only when SRAM output is unused or correct
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val d_pause = d_read && d_ram_valid && d_need_fix
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in.d.valid := d_full && !d_pause
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in.a.ready := !d_full || (in.d.ready && !d_pause && !d_wb)
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val a_legal = Bool(errors.isEmpty) || address.contains(in.a.bits.address)
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val a_address = Cat(addrBits.reverse)
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val a_read = in.a.bits.opcode === TLMessages.Get
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val a_data = Vec(Seq.tabulate(lanes) { i => in.a.bits.data(eccBytes*8*(i+1)-1, eccBytes*8*i) })
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/*
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val a_sublane = Seq.tabulate(lanes) { i =>
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val upd = in.a.bits.mask(eccBytes*(i+1)-1, eccBytes*i)
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upd.orR && !upd.andR
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}.reduce(_ || _)
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*/
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val a_sublane = if (eccBytes == 1) Bool(false) else
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in.a.bits.opcode === TLMessages.PutPartialData ||
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in.a.bits.size < UInt(log2Ceil(eccBytes))
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val a_ren = a_read || a_sublane
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val a_lanes = Seq.tabulate(lanes) { i => in.a.bits.mask(eccBytes*(i+1)-1, eccBytes*i).orR }
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when (in.d.fire()) { d_full := Bool(false) }
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d_ram_valid := Bool(false)
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d_rmw_mask := UInt(0)
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when (in.a.fire()) {
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d_read := read
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d_size := in.a.bits.size
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d_source := in.a.bits.source
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d_legal := a_legal
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d_full := Bool(true)
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d_ram_valid := a_ren && a_legal
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d_size := in.a.bits.size
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d_source := in.a.bits.source
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d_legal := a_legal
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d_read := a_read
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d_address := a_address
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d_rmw_mask := UInt(0)
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when (!a_read && a_sublane) {
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d_rmw_mask := in.a.bits.mask
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d_rmw_data := in.a.bits.data
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}
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d_held_error:= Bool(false)
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}
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// exactly this pattern is required to get a RWM memory
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when (in.a.fire() && !read && a_legal) {
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mem.write(memAddress, wdata, in.a.bits.mask.toBools)
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}
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val ren = in.a.fire() && read
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rdata := mem.readAndHold(memAddress, ren)
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// SRAM arbitration
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val a_fire = in.a.fire() && a_legal
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val wen = d_wb || (a_fire && !a_ren)
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// val ren = !d_wb && (a_fire && a_ren)
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val ren = !wen && a_fire // help Chisel infer a RW-port
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val addr = Mux(d_wb, d_address, a_address)
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val sel = Mux(d_wb, Vec(d_wb_lanes), Vec(a_lanes))
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val dat = Mux(d_wb, d_wb_data, a_data)
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val poison = Mux(d_wb, Vec(d_wb_poison), Vec.fill(lanes) { Bool(false) })
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val coded = Vec((dat zip poison) map { case (d, p) =>
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if (code.canDetect) code.encode(d, p) else code.encode(d)
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})
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d_raw_data := mem.read(addr, ren)
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when (wen) { mem.write(addr, coded, sel) }
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// Tie off unused channels
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in.b.valid := Bool(false)
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@ -88,10 +175,12 @@ object TLRAM
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cacheable: Boolean = true,
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executable: Boolean = true,
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beatBytes: Int = 4,
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eccBytes: Int = 1,
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devName: Option[String] = None,
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errors: Seq[AddressSet] = Nil)(implicit p: Parameters): TLInwardNode =
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errors: Seq[AddressSet] = Nil,
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code: Code = new IdentityCode)(implicit p: Parameters): TLInwardNode =
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{
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val ram = LazyModule(new TLRAM(address, cacheable, executable, beatBytes, devName, errors))
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val ram = LazyModule(new TLRAM(address, cacheable, executable, beatBytes, eccBytes, devName, errors, code))
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ram.node
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}
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}
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@ -115,3 +204,20 @@ class TLRAMSimpleTest(ramBeatBytes: Int, txns: Int = 5000, timeout: Int = 500000
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val dut = Module(LazyModule(new TLRAMSimple(ramBeatBytes, txns)).module)
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io.finished := dut.io.finished
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}
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class TLRAMECC(ramBeatBytes: Int, eccBytes: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
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val fuzz = LazyModule(new TLFuzzer(txns))
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val model = LazyModule(new TLRAMModel("SRAMSimple"))
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val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes, eccBytes = eccBytes, code = new SECDEDCode))
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ram.node := TLDelayer(0.25) := model.node := fuzz.node
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lazy val module = new LazyModuleImp(this) with UnitTestModule {
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io.finished := fuzz.module.io.finished
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}
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}
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class TLRAMECCTest(ramBeatBytes: Int, eccBytes: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
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val dut = Module(LazyModule(new TLRAMECC(ramBeatBytes, eccBytes, txns)).module)
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io.finished := dut.io.finished
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}
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@ -50,7 +50,10 @@ class WithTLSimpleUnitTests extends Config((site, here, up) => {
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Module(new TLRR1Test( txns= 3*txns, timeout=timeout)),
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Module(new TLRAMRationalCrossingTest(txns= 3*txns, timeout=timeout)),
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Module(new TLRAMAsyncCrossingTest( txns= 5*txns, timeout=timeout)),
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Module(new TLRAMAtomicAutomataTest( txns=10*txns, timeout=timeout)) ) }
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Module(new TLRAMAtomicAutomataTest( txns=10*txns, timeout=timeout)),
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Module(new TLRAMECCTest(8, 4, txns=15*txns, timeout=timeout)),
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Module(new TLRAMECCTest(4, 1, txns=15*txns, timeout=timeout)),
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Module(new TLRAMECCTest(1, 1, txns=15*txns, timeout=timeout)) ) }
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})
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class WithTLWidthUnitTests extends Config((site, here, up) => {
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