subsystem: add TLIdentity.gen and make wrappers more flexible
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eaa908d44f
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@ -56,17 +56,12 @@ class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWr
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}
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}
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def toDRAMController(
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def toDRAMController[D,U,E,B <: Data](
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name: Option[String] = None,
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buffer: BufferParams = BufferParams.none)
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(gen: => TLInwardNode) {
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to("memory_controller" named name) { gen := bufferTo(buffer) }
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}
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def toDRAMControllerPort[D,U,E,B <: Data](
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name: Option[String] = None,
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buffer: BufferParams = BufferParams.none)
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(gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B]): OutwardNodeHandle[D,U,E,B] = {
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(gen: => NodeHandle[
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TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,
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D,U,E,B] = TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
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to("memory_controller" named name) { gen := bufferTo(buffer) }
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}
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@ -33,34 +33,42 @@ class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCross
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private def fixedWidthTo(buffer: BufferParams): TLOutwardNode =
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TLWidthWidget(params.beatBytes) :*= bufferTo(buffer)
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def toSlave(
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def toSlave[D,U,E,B <: Data](
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name: Option[String] = None,
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buffer: BufferParams = BufferParams.none)
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(gen: => TLNode): TLOutwardNode = {
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(gen: => NodeHandle[
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TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,
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D,U,E,B] = TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
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to("slave" named name) { gen :*= bufferTo(buffer) }
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}
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def toVariableWidthSlave(
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def toVariableWidthSlave[D,U,E,B <: Data](
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name: Option[String] = None,
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buffer: BufferParams = BufferParams.none)
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(gen: => TLNode): TLOutwardNode = {
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(gen: => NodeHandle[
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TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,
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D,U,E,B] = TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
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to("slave" named name) {
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gen :*= fragmentTo(params.beatBytes, params.blockBytes, buffer)
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}
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}
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def toFixedWidthSlave(
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def toFixedWidthSlave[D,U,E,B <: Data](
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name: Option[String] = None,
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buffer: BufferParams = BufferParams.none)
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(gen: => TLNode): TLOutwardNode = {
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(gen: => NodeHandle[
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TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,
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D,U,E,B] = TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
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to("slave" named name) { gen :*= fixedWidthTo(buffer) }
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}
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def toFixedWidthSingleBeatSlave(
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def toFixedWidthSingleBeatSlave[D,U,E,B <: Data](
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widthBytes: Int,
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name: Option[String] = None,
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buffer: BufferParams = BufferParams.none)
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(gen: => TLNode): TLOutwardNode = {
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(gen: => NodeHandle[
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TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,
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D,U,E,B] = TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
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to("slave" named name) {
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gen :*= TLFragmenter(widthBytes, params.blockBytes) :*= fixedWidthTo(buffer)
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}
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@ -76,6 +84,14 @@ class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCross
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}
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}
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def toFixedWidthPort[D,U,E,B <: Data](
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name: Option[String] = None,
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buffer: BufferParams = BufferParams.none)
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(gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B]): OutwardNodeHandle[D,U,E,B] = {
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to("port" named name) { gen := fixedWidthTo(buffer) }
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}
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def fromSystemBus(
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arithmetic: Boolean = true,
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buffer: BufferParams = BufferParams.default)
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@ -52,7 +52,7 @@ trait HasMasterAXI4MemPort { this: BaseSubsystem =>
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})
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memBuses.map { m =>
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mem_axi4 := m.toDRAMControllerPort(Some(portName)) {
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mem_axi4 := m.toDRAMController(Some(portName)) {
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(AXI4UserYanker() := AXI4IdIndexer(params.idBits) := TLToAXI4())
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}
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}
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@ -47,7 +47,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
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def toSplitSlave(name: Option[String] = None)
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(gen: => TLNode): TLOutwardNode = {
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to("slave" named name) { gen :*= master_splitter.node }
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to("slave" named name) { gen :=* master_splitter.node }
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}
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def toFixedWidthSlave(
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@ -66,12 +66,8 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
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}
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}
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def fromCoherentChip(gen: => TLNode): TLInwardNode = {
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from("CoherentChip") { inwardNode :=* gen }
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}
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def fromFrontBus(gen: => TLNode): TLInwardNode = {
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from("FrontBus") { master_splitter.node :=* gen }
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from("front_bus") { master_splitter.node :=* gen }
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}
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def fromTile(
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@ -104,15 +100,27 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
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}
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}
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def fromCoherentMaster(
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name: Option[String] = None,
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buffers: Int = 0)
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(gen: => TLNode): TLInwardNode = {
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from("coherent_master" named name) {
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(inwardNode
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:=* TLFIFOFixer(TLFIFOFixer.all)
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:=* TLBuffer.chain(buffers).reduce(_ :=* _)
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:=* gen)
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}
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}
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def fromMaster(
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name: Option[String] = None,
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buffers: Int = 0)
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(gen: => TLNode): TLInwardNode = {
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from("master" named name) {
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(List(
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master_splitter.node,
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TLFIFOFixer(TLFIFOFixer.all)) ++
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TLBuffer.chain(buffers)).reduce(_ :=* _) :=* gen
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(master_splitter.node
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:=* TLFIFOFixer(TLFIFOFixer.all)
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:=* TLBuffer.chain(buffers).reduce(_ :=* _)
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:=* gen)
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}
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}
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}
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@ -54,3 +54,10 @@ trait HasTLXbarPhy { this: TLBusWrapper =>
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protected def inwardNode: TLInwardNode = xbar.node
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protected def outwardNode: TLOutwardNode = xbar.node
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}
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object TLIdentity {
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def gen: TLNode = {
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val passthru = TLIdentityNode()
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passthru
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}
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}
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