riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Add BusErrorUnit RegFieldDesc

Browse Source
This commit is contained in:
Andrew Waterman 2018-03-02 17:25:13 -08:00
parent 8c6e745653
commit 644ba6dafa
1 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/main/scala/rocket/BusErrorUnit.scala
View File

@ -68,17 +68,17 @@ class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams)(implicit
io.interrupt := (accrued.asUInt & local_interrupt.asUInt).orR
int_out(0) := (accrued.asUInt & global_interrupt.asUInt).orR
def reg(r: UInt) = RegField.bytes(r, (r.getWidth + 7)/8)
def reg(v: Vec[Bool]) = v.map(r => RegField(1, r))
def reg(r: UInt, name: String, reset: Option[BigInt]) = RegFieldGroup(name, None, RegField.bytes(r, (r.getWidth + 7)/8, Some(RegFieldDesc(name, "", reset=reset))))
def reg(v: Vec[Bool], name: String, reset: Option[BigInt]) = RegFieldGroup(name, None, v.map(r => RegField(1, r, RegFieldDesc(name, "", reset=reset))))
def numberRegs(x: Seq[Seq[RegField]]) = x.zipWithIndex.map { case (f, i) => (i * regWidth / 8) -> f }
node.regmap(numberRegs(Seq(
reg(cause),
reg(value),
reg(enable),
reg(global_interrupt),
reg(accrued),
reg(local_interrupt))):_*)
reg(cause, "cause", Some(BigInt(0))),
reg(value, "value", None),
reg(enable, "enable", Some(sources.zipWithIndex.map { case (s, i) => BigInt(s.size) << i }.sum)),
reg(global_interrupt, "plic_interrupt", Some(BigInt(0))),
reg(accrued, "accrued", Some(BigInt(0))),
reg(local_interrupt, "local_interrupt", Some(BigInt(0))))):_*)
// hardwire mask bits for unsupported sources to 0
for ((s, i) <- sources.zipWithIndex; if s.isEmpty) {