Fix debug trigger point for stores
In Rocket, debug triggers are supposed to happen before a store occurs, rather than after. Previously, we reported the exception on the store's PC, but the store occurred anyway. This probably hasn't been problematic in practice because most stores are idempotent.
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@ -427,14 +427,14 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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val mem_breakpoint = (mem_reg_load && bpu.io.xcpt_ld) || (mem_reg_store && bpu.io.xcpt_st)
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val mem_debug_breakpoint = (mem_reg_load && bpu.io.debug_ld) || (mem_reg_store && bpu.io.debug_st)
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val (mem_new_xcpt, mem_new_cause) = checkExceptions(List(
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(mem_debug_breakpoint, UInt(CSR.debugTriggerCause)),
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(mem_breakpoint, UInt(Causes.breakpoint)),
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(mem_npc_misaligned, UInt(Causes.misaligned_fetch))))
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val (mem_ldst_xcpt, mem_ldst_cause) = checkExceptions(List(
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(mem_debug_breakpoint, UInt(CSR.debugTriggerCause)),
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(mem_breakpoint, UInt(Causes.breakpoint))))
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val (mem_xcpt, mem_cause) = checkExceptions(List(
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(mem_reg_xcpt_interrupt || mem_reg_xcpt, mem_reg_cause),
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(mem_reg_valid && mem_new_xcpt, mem_new_cause)))
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(mem_reg_valid && mem_npc_misaligned, UInt(Causes.misaligned_fetch)),
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(mem_reg_valid && mem_ldst_xcpt, mem_ldst_cause)))
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val memCoverCauses = (exCoverCauses ++ List(
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(CSR.debugTriggerCause, "DEBUG_TRIGGER"),
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@ -677,7 +677,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out)
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io.dmem.invalidate_lr := wb_xcpt
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io.dmem.s1_data.data := (if (fLen == 0) mem_reg_rs2 else Mux(mem_ctrl.fp, Fill((xLen max fLen) / fLen, io.fpu.store_data), mem_reg_rs2))
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io.dmem.s1_kill := killm_common || mem_breakpoint
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io.dmem.s1_kill := killm_common || mem_ldst_xcpt
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io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common
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io.rocc.exception := wb_xcpt && csr.io.status.xs.orR
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