riscv/rocket-chip
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DefaultRV32Config should provide fdiv/fsqrt

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This is a holdover from before we had built the functional unit.
This commit is contained in:
Andrew Waterman 2018-02-20 15:44:30 -08:00
parent b487448961
commit d4fb7ad6a2
1 changed files with 1 additions and 2 deletions
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src/main/scala/coreplex/Configs.scala
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@ -165,8 +165,7 @@ class WithRV32 extends Config((site, here, up) => {
case XLen => 32
case RocketTilesKey => up(RocketTilesKey, site) map { r =>
r.copy(core = r.core.copy(
mulDiv = Some(MulDivParams(mulUnroll = 8)),
fpu = r.core.fpu.map(_.copy(divSqrt = false))))
mulDiv = Some(MulDivParams(mulUnroll = 8))))
}
})