subsystem: add some inter-wrapper buffer params
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@ -37,11 +37,11 @@ abstract class BaseSubsystem(implicit p: Parameters) extends BareSubsystem {
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val fbus = LazyModule(new FrontBus(p(FrontBusKey)))
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// The sbus masters the pbus; here we convert TL-UH -> TL-UL
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pbus.fromSystemBus() { sbus.toPeripheryBus() { pbus.crossTLIn } }
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pbus.fromSystemBus { sbus.toPeripheryBus { pbus.crossTLIn } }
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// The fbus masters the sbus; both are TL-UH or TL-C
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FlipRendering { implicit p =>
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fbus.toSystemBus() { sbus.fromFrontBus { fbus.crossTLOut } }
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fbus.toSystemBus { sbus.fromFrontBus { fbus.crossTLOut } }
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}
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// The sbus masters the mbus; here we convert TL-C -> TL-UH
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@ -8,14 +8,19 @@ import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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case class FrontBusParams(beatBytes: Int, blockBytes: Int) extends HasTLBusParams
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case class FrontBusParams(
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beatBytes: Int,
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blockBytes: Int,
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sbusCrossing: SubsystemClockCrossing = SynchronousCrossing(),
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sbusBuffer: BufferParams = BufferParams.default) extends HasTLBusParams
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case object FrontBusKey extends Field[FrontBusParams]
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class FrontBus(params: FrontBusParams, val crossing: SubsystemClockCrossing = SynchronousCrossing())
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class FrontBus(params: FrontBusParams)
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(implicit p: Parameters) extends TLBusWrapper(params, "front_bus")
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with HasTLXbarPhy
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with HasCrossing {
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val crossing = params.sbusCrossing
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def fromPort[D,U,E,B <: Data]
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(name: Option[String] = None, buffers: Int = 1)
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@ -39,7 +44,7 @@ class FrontBus(params: FrontBusParams, val crossing: SubsystemClockCrossing = Sy
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from("coherent_subsystem") { inwardNode :=* gen }
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}
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def toSystemBus(buffer: BufferParams = BufferParams.none)(gen: => TLInwardNode) {
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to("sbus") { gen :=* TLBuffer(buffer) :=* outwardNode }
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def toSystemBus(gen: => TLInwardNode) {
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to("sbus") { gen :=* TLBuffer(params.sbusBuffer) :=* outwardNode }
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}
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}
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@ -12,6 +12,7 @@ case class PeripheryBusParams(
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beatBytes: Int,
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blockBytes: Int,
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arithmeticAtomics: Boolean = true,
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bufferAtomics: BufferParams = BufferParams.default,
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sbusCrossingType: SubsystemClockCrossing = SynchronousCrossing(), // relative to sbus
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frequency: BigInt = BigInt(100000000) // 100 MHz as default bus frequency
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) extends HasTLBusParams
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@ -92,7 +93,7 @@ class PeripheryBus(params: PeripheryBusParams)
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def fromSystemBus(gen: => TLOutwardNode) {
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from("sbus") {
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(inwardNode
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:*= TLBuffer(BufferParams.default)
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:*= TLBuffer(params.bufferAtomics)
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:*= TLAtomicAutomata(arithmetic = params.arithmeticAtomics)
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:*= gen)
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}
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@ -8,7 +8,10 @@ import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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case class SystemBusParams(beatBytes: Int, blockBytes: Int) extends HasTLBusParams
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case class SystemBusParams(
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beatBytes: Int,
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blockBytes: Int,
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pbusBuffer: BufferParams = BufferParams.none) extends HasTLBusParams
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case object SystemBusKey extends Field[SystemBusParams]
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@ -23,13 +26,12 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
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def busView = master_splitter.node.edges.in.head
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def toPeripheryBus(buffer: BufferParams = BufferParams.none)
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(gen: => TLNode): TLOutwardNode = {
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def toPeripheryBus(gen: => TLNode): TLOutwardNode = {
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to("pbus") {
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(gen
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:= TLFIFOFixer(TLFIFOFixer.all)
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:= TLWidthWidget(params.beatBytes)
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:= bufferTo(buffer))
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:= bufferTo(params.pbusBuffer))
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}
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}
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@ -52,7 +54,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
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}
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def toFixedWidthSlave[D,U,E,B <: Data]
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(name: Option[String] = None, buffer: BufferParams = BufferParams.none)
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(name: Option[String] = None, buffer: BufferParams = BufferParams.default)
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(gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] =
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TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
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to("slave" named name) { gen :*= fixedWidthTo(buffer) }
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