debug: get beatBytes from pbus, not XLen
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@ -7,7 +7,6 @@ import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.rocket.Instructions
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import freechips.rocketchip.tile.XLen
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.util._
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@ -424,7 +423,7 @@ class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends La
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}
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}
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class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p: Parameters) extends LazyModule
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class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule
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{
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val dmiNode = TLRegisterNode(
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@ -438,7 +437,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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val tlNode = TLRegisterNode(
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address=Seq(AddressSet(0, 0xFFF)), // This is required for correct functionality, it's not configurable.
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device=device,
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beatBytes=p(XLen)/8,
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beatBytes=beatBytes,
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executable=true
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)
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@ -1029,9 +1028,9 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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// Handles the synchronization of dmactive, which is used as a synchronous reset
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// inside the Inner block.
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// Also is the Sink side of hartsel & resumereq fields of DMCONTROL.
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class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int)(implicit p: Parameters) extends LazyModule{
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class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule{
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val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents))
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val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents, beatBytes))
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val dmiXing = LazyModule(new TLAsyncCrossingSink(depth=1))
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val dmiNode = dmiXing.node
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val tlNode = dmInner.tlNode
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@ -1060,14 +1059,14 @@ class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int)(implici
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* because the Clock must run when tlClock isn't running or tlReset is asserted.
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*/
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class TLDebugModule(implicit p: Parameters) extends LazyModule {
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class TLDebugModule(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
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val device = new SimpleDevice("debug-controller", Seq("sifive,debug-013","riscv,debug-013")){
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override val alwaysExtended = true
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}
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val dmOuter = LazyModule(new TLDebugModuleOuterAsync(device)(p))
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val dmInner = LazyModule(new TLDebugModuleInnerAsync(device, () => {dmOuter.dmOuter.intnode.edges.out.size})(p))
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val dmInner = LazyModule(new TLDebugModuleInnerAsync(device, () => {dmOuter.dmOuter.intnode.edges.out.size}, beatBytes)(p))
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val node = dmInner.tlNode
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val intnode = dmOuter.intnode
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@ -29,7 +29,7 @@ class DebugIO(implicit val p: Parameters) extends ParameterizedBundle()(p) with
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trait HasPeripheryDebug extends HasPeripheryBus {
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val module: HasPeripheryDebugModuleImp
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val debug = LazyModule(new TLDebugModule())
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val debug = LazyModule(new TLDebugModule(pbus.beatBytes))
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debug.node := pbus.toVariableWidthSlaves
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}
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