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debug: get beatBytes from pbus, not XLen

This commit is contained in:
Andrew Waterman 2018-02-20 15:37:36 -08:00
parent 62f9b84439
commit bd29184e11
2 changed files with 7 additions and 8 deletions
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13
src/main/scala/devices/debug/Debug.scala
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@ -7,7 +7,6 @@ import freechips.rocketchip.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.rocket.Instructions
import freechips.rocketchip.tile.XLen
import freechips.rocketchip.tilelink._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.util._
@ -424,7 +423,7 @@ class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends La
}
}
class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p: Parameters) extends LazyModule
class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule
{
val dmiNode = TLRegisterNode(
@ -438,7 +437,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
val tlNode = TLRegisterNode(
address=Seq(AddressSet(0, 0xFFF)), // This is required for correct functionality, it's not configurable.
device=device,
beatBytes=p(XLen)/8,
beatBytes=beatBytes,
executable=true
)
@ -1029,9 +1028,9 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
// Handles the synchronization of dmactive, which is used as a synchronous reset
// inside the Inner block.
// Also is the Sink side of hartsel & resumereq fields of DMCONTROL.
class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int)(implicit p: Parameters) extends LazyModule{
class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule{
val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents))
val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents, beatBytes))
val dmiXing = LazyModule(new TLAsyncCrossingSink(depth=1))
val dmiNode = dmiXing.node
val tlNode = dmInner.tlNode
@ -1060,14 +1059,14 @@ class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int)(implici
* because the Clock must run when tlClock isn't running or tlReset is asserted.
*/
class TLDebugModule(implicit p: Parameters) extends LazyModule {
class TLDebugModule(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
val device = new SimpleDevice("debug-controller", Seq("sifive,debug-013","riscv,debug-013")){
override val alwaysExtended = true
}
val dmOuter = LazyModule(new TLDebugModuleOuterAsync(device)(p))
val dmInner = LazyModule(new TLDebugModuleInnerAsync(device, () => {dmOuter.dmOuter.intnode.edges.out.size})(p))
val dmInner = LazyModule(new TLDebugModuleInnerAsync(device, () => {dmOuter.dmOuter.intnode.edges.out.size}, beatBytes)(p))
val node = dmInner.tlNode
val intnode = dmOuter.intnode

2
src/main/scala/devices/debug/Periphery.scala
View File

@ -29,7 +29,7 @@ class DebugIO(implicit val p: Parameters) extends ParameterizedBundle()(p) with
trait HasPeripheryDebug extends HasPeripheryBus {
val module: HasPeripheryDebugModuleImp
val debug = LazyModule(new TLDebugModule())
val debug = LazyModule(new TLDebugModule(pbus.beatBytes))
debug.node := pbus.toVariableWidthSlaves
}