support testing RV32D configs
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@ -57,15 +57,14 @@ object Generator extends GeneratorApp {
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val env = if (vm) List("p","v") else List("p")
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coreParams.fpu foreach { case cfg =>
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if (xlen == 32) {
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TestGeneration.addSuites(env.map(rv32ufNoDiv))
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TestGeneration.addSuites(env.map(rv32uf))
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if (cfg.fLen >= 64)
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TestGeneration.addSuites(env.map(rv32ud))
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} else {
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TestGeneration.addSuite(rv32udBenchmarks)
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TestGeneration.addSuites(env.map(rv64ufNoDiv))
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TestGeneration.addSuites(env.map(rv64udNoDiv))
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if (cfg.divSqrt) {
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TestGeneration.addSuites(env.map(rv64uf))
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TestGeneration.addSuites(env.map(rv64uf))
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if (cfg.fLen >= 64)
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TestGeneration.addSuites(env.map(rv64ud))
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}
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}
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}
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if (coreParams.useAtomics) {
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@ -143,13 +143,12 @@ object DefaultTestSuites {
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val rv64ufNames = LinkedHashSet("ldst", "move", "fcmp", "fcvt", "fcvt_w", "fclass", "fadd", "fdiv", "fmin", "fmadd")
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val rv64uf = new AssemblyTestSuite("rv64uf", rv64ufNames)(_)
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val rv64ufNoDiv = new AssemblyTestSuite("rv64uf", rv64ufNames - "fdiv")(_)
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val rv32ufNoDiv = new AssemblyTestSuite("rv32uf", rv64ufNames - "fdiv")(_)
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val rv32uf = new AssemblyTestSuite("rv32uf", rv64ufNames)(_)
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val rv32ud = new AssemblyTestSuite("rv32ud", rv64ufNames - "move")(_)
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val rv64udNames = rv64ufNames + "structural"
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val rv64ud = new AssemblyTestSuite("rv64ud", rv64udNames)(_)
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val rv64udNoDiv = new AssemblyTestSuite("rv64ud", rv64udNames - "fdiv")(_)
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val rv64siNames = rv32siNames
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val rv64si = new AssemblyTestSuite("rv64si", rv64siNames)(_)
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