a59ba39310
bump submodule for fpga-zynq
2015-05-21 11:26:57 -07:00
38edbc78e5
Merge pull request #5 from amsharifian/master
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Update Makefile
2015-05-21 11:24:25 -07:00
6a9390c50e
Avoid spurious D$ assertion failures
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For the Rocket pipeline, this fix is needless and the problem is that the
assertion is too conservative, but I solved it this way to avoid problems
for other plausible use cases where physical and virtual accesses are
intermixed.
2015-05-19 03:00:53 -07:00
f460cb6c54
Update to privileged architecture 1.7
2015-05-19 02:32:21 -07:00
254498042a
Fix Split for 0-width wires
2015-05-18 18:23:17 -07:00
d31b26c342
Clean up handling of icache's io.cpu.npc signal
2015-05-18 18:22:48 -07:00
c202449e34
first version NASTI IOs
2015-05-14 15:29:49 -07:00
90c9ee7b04
fix unalloc putblocks
2015-05-14 12:37:35 -07:00
a7fa77c7fc
track operand size for Gets
2015-05-13 23:28:18 -07:00
172c372d3e
L2 alloc cleanup
2015-05-12 17:14:06 -07:00
5fdae2cb61
Merge branch 'master' of github.com:ucb-bar/uncore
2015-05-07 16:18:23 -07:00
fc883b5049
rm index.html
2015-05-07 16:17:40 -07:00
8362eba00f
Merge branch 'gh-pages'
2015-05-07 16:16:13 -07:00
aec24cf1a7
readme
2015-05-07 16:16:07 -07:00
62b6f24798
Delete TileLink0.3.1Specification.pdf
2015-05-07 15:43:06 -07:00
90ced93eeb
Merge branch 'master' into gh-pages
2015-05-07 12:35:14 -07:00
4cef8c9cd4
Added MemIOArbiter
2015-05-07 10:55:38 -07:00
b09832f1b5
ICache now returns the "next PC" signal.
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useful for other modules that need access to the fetch PC on the
cycle it is sent to the SRAM.
2015-05-07 04:53:05 -07:00
c746ef8702
fix bug in rocc port resp for FPtoInt instructions
2015-05-04 11:20:55 -07:00
8832b454ce
add plugins to make scala doc site and publish to ghpages
2015-04-29 15:34:56 -07:00
1e05fc0525
First pages commit
2015-04-29 13:18:26 -07:00
b9fb1bb46e
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
2015-04-29 00:43:53 -07:00
3673295d03
network shim cleanup
2015-04-27 16:59:30 -07:00
09e30041ed
Voluntary Writeback tracker rewrite
2015-04-27 12:56:33 -07:00
a37fad2e9b
Merge branch 'retimeable-frontend' into rocc-fpu-port
2015-04-22 14:23:52 -07:00
1f410ac42c
move fetch buffer into frontend to allow retiming
2015-04-22 11:26:03 -07:00
11b5222d01
Refactored WritebackUnit
2015-04-21 22:23:04 -07:00
4c7969b2b3
Metadata docs and api cleanup
2015-04-20 16:32:09 -07:00
a315fe93c1
simplify ClientMetadata.makeRelease
2015-04-20 10:46:24 -07:00
f66a9fd7a6
simplify ClientMetadata.makeRelease
2015-04-20 10:46:02 -07:00
6d40a61060
TileLink scala doc and parameter renaming
2015-04-19 22:06:44 -07:00
ca5b3d988d
Merge branch 'master' into rocc-fpu-port
2015-04-19 15:00:00 -07:00
3048f4785a
HeaderlessTileLinkIO -> ClientTileLinkIO
2015-04-17 16:56:53 -07:00
ba7a8b1752
TileLink refactor; TileLinkPorts now available. L2Banks no longer have unique ids (suitable for hierarhical P&R).
2015-04-17 16:55:20 -07:00
73fa28521d
Merge branch 'master' of github.com:ucb-bar/rocket into rocc-fpu-port
2015-04-16 15:22:08 -07:00
ce3271aef2
refactor LNClients and LNManagers
2015-04-15 15:48:36 -07:00
49f1c0aa7b
moved ecc lib to uncore
2015-04-13 15:58:10 -07:00
91e882e3f8
Use HeaderlessTileLinkIO
2015-04-13 15:58:10 -07:00
90f800d87d
Grant bugfixes and more comments
2015-04-13 15:57:06 -07:00
24bb032ede
Merge pull request #7 from ccelio/master
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Rocket front-end can now fetch 4 instructions; added assert to dcache; refactoring
2015-04-12 19:18:23 -07:00
517d0d4b89
feedback on PR
2015-04-12 18:44:03 -07:00
4d6ebded02
Added assert to nbdcache
2015-04-11 02:58:34 -07:00
a564f08702
Rename dmem.sret signal to more accurate invalidate_lr
2015-04-11 02:26:33 -07:00
8fc2d38ca9
Removed unnecessary signal in CSRIO
2015-04-11 02:20:34 -07:00
2f88c5ca9d
Renamed PCR to CSR
2015-04-11 02:16:44 -07:00
11dbd4221a
Fixed front-end to support four-wide fetch.
2015-04-10 17:53:47 -07:00
bd72db92c1
update rocc port to use fdiv/sqrt
2015-04-07 15:02:02 -07:00
879a4a0bcd
Update Makefile
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Change default shell to bash shell.
2015-04-06 15:05:43 -07:00
887a8de189
Merge branch 'master' of github.com:ucb-bar/rocket into rocc-fpu-port
2015-04-06 13:48:44 -07:00
3cf1778c92
moved ecc lib to uncore, l2 checks for partial write masks when ecc is enabled
2015-04-06 12:22:23 -07:00
