riscv/rocket-chip
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578 Commits

Author SHA1 Message Date
Palmer Dabbelt
e2185d40f6 Avoid right-shift by larger that the bit width 
FIRRTL bails out on this.  There's an outstanding bug, this is just a
workaround.  See https://github.com/ucb-bar/firrtl/issues/69
 2016-03-10 17:37:40 -08:00
Palmer Dabbelt
8c7e29eacd Avoid generating 0-width UInts 
Chisel3 requires a 1-bit width to represent UInt(0).
 2016-03-10 17:37:40 -08:00
Andrew Waterman
2eafc4c8f3 Extend AMOALU to support RV32 2016-03-10 17:32:23 -08:00
Andrew Waterman
c28d115b30 Chisel3 compatibility fix 2016-03-10 17:32:23 -08:00
Henry Cook
93773a4496 Refactor L2 transaction trackers to each be capable of processing Voluntary Writebacks. 
To elide several races between reading and writing the metadata array for different types of transactions, all L2XactTrackers can now sink Voluntary Releases (writebacks from the L1 in the current implementation). These writebacks are merged with the ongoing transaction, and the merging tracker supplies an acknowledgment of the writeback in addition to its ongoing activities. This change involved another refactoring of the control logic for allocating new trackers and routing incoming Acquires and Releases. BroadcastHub uses the new routing logic, but still processes all voluntary releases through the VoluntaryReleaseTracker (not a problem because there are no metadata update races).

Closes #18
Closes #20
 2016-03-10 17:14:34 -08:00
Andrew Waterman
36f2e6504c Fix width of NastiROM rows, preventing out-of-range extraction 2016-03-03 16:57:16 -08:00
Henry Cook
7eef3393f1 fix bug resulting in different g_types on tail beats in L2CacheBank.io.inner.grant 2016-03-02 14:11:45 -08:00
Henry Cook
57370bdf49 first and last on HasTileLinkData 2016-03-02 14:11:39 -08:00
Palmer Dabbelt
4acdc67485 Add an assertion in the NastiIOTileLink converter 
This uses an reorder queue but doesn't check to ensure that the data it fetches
from the queue is actually in the queue before using it.  It seems that during
correct operation this never breaks, but I'm trying to get the backup memory
port working again and this assertion fails with it enabled (without the
assertion the core just gets a bogus data beat dies).

Closes #16
 2016-03-01 12:23:32 -08:00
Albert Magyar
ab30983aa9 Add support for per-way cache metadata 
Exposes new parameter field SplitMetadata to determine whether the metadata array in a particular cache is stored in a single SeqMem or with one SeqMem per way.

Closes #14
 2016-03-01 12:19:42 -08:00
Howard Mao
6d984273b7 finally fix all release assertions ... hopefully 2016-02-29 15:22:24 -08:00
John Wright
6095e7361e Move N_CORES and MMIO_BASE to SCRFile instance in RocketChip 2016-02-27 16:19:25 -08:00
Palmer Dabbelt
ebffd69b8e Provide both __OFFSET and __PADDR for SCR entries 
This was recently changed to write out physical addresses for SCR file entries,
but to bring up the chip we need SCR offsets so we can write the uncore SCR
file over HTIF.  This changes the map generator to generate both.

Without this change things happened to work anyway because the high bits were
getting dropped by the SCR file.
 2016-02-25 21:48:32 -08:00
John Wright
19420cd5df add utility overloads of SCRIO.attach, pass base address so that generated c header is correct, and print debug messages/header in hex instead of decimal 2016-02-24 15:26:55 -08:00
Howard Mao
8873222e42 fix cache release assertion 2016-02-23 16:03:51 -08:00
Henry Cook
929d8e31f7 refactor ready/valid logic for routing release messages in the l2 2016-02-19 16:30:26 -08:00
Howard Mao
f97bd70df5 add NastiIO to HostIO converter 2016-02-19 11:21:23 -08:00
Palmer Dabbelt
1ac9f59b31 Allow SCR files to be enumerated in C headers 
Right now there's no way to ensure that SCR addresses don't conflict within
RocketChip.  Since upstream only has one of them this isn't a big deal, but we
want to add a whole bunch more to control all the IP on Hurricane.

This patch adds some Scala code to allocate registers inside the SCR file,
ensure they don't conflict, to provide names for SCRs, attach registers to the
SCR file, and generate a C header file that contains the addresses of every SCR
on a chip.

With this patch we'll be able to get rid of that constant in the testbench.
This also allows us to kill one of the Raven diffs, which is does pretty much
the same thing (just in a second SCR file, and hacked in).
 2016-02-17 14:21:12 -08:00
Howard Mao
53ad8387cc add NASTI to TL converter 2016-02-10 11:06:52 -08:00
Howard Mao
2825b2d645 make sure TL to NASTI converter handles MT_WU 2016-02-10 11:06:41 -08:00
Howard Mao
66e9cc8c82 make sure CSR width is parameterizable 2016-02-02 12:49:58 -08:00
Howard Mao
adaec18bec add TL manager for MMIO requests 2016-02-02 12:49:58 -08:00
Howard Mao
c1fe188c81 some fixes to RTC 2016-02-02 12:49:58 -08:00
Howard Mao
ba94010928 DMA requests should go through MMIO 2016-02-02 12:49:58 -08:00
Howard Mao
0dc8cd5b11 move ReorderQueue and DecoupledHelper to junctions 2016-01-21 15:36:22 -08:00
Andrew Waterman
2946bc928e Avoid muxing between bundles of different size 2016-01-16 19:01:24 -08:00
Howard Mao
4ff1aea288 fix more Chisel3 deprecations 2016-01-14 14:55:45 -08:00
Andrew Waterman
0b90b8fe5f Avoid zero-width wire case :-/ 2016-01-12 15:32:29 -08:00
Andrew Waterman
a953ff384a Chisel3 compatibility: use more concrete types 2016-01-12 15:32:14 -08:00
Howard Mao
c81745eb8e lowercase SMI to Smi 2016-01-11 16:18:44 -08:00
Howard Mao
d0a14c6de9 separate TileLink converter/wrapper/unwrapper/narrower into separate file 2016-01-11 16:14:56 -08:00
Howard Mao
46069ea13b implement streaming DMA functionality 2016-01-06 21:37:56 -08:00
Howard Mao
872b162e1b implement DMA engine 2015-12-16 21:27:31 -08:00
Howard Mao
8a61177224 generalize TwoWayCounter 2015-12-16 21:07:30 -08:00
Howard Mao
a48237f36d get rid of the rest of the PutBlock special casing in L2 2015-12-16 20:56:29 -08:00
Albert Magyar
922b1adc9c Add optional PLRU replacement to the L2 2015-12-16 10:00:56 -08:00
Howard Mao
ddc79674f9 fix some issues with cache request merging 2015-12-15 21:31:02 -08:00
Howard Mao
e71293e2ae fix bug in narrower logic 2015-12-06 02:58:12 -08:00
Sagar Karandikar
93aa370b87 yunsup's fix for dgemm-opt assertion failure 2015-12-03 14:03:10 -08:00
Andrew Waterman
e52685f2e9 Fix LoadGen zero flag 2015-11-25 20:52:30 -08:00
Andrew Waterman
27df04354f Add ROM with NASTI interface 2015-11-25 20:04:31 -08:00
Andrew Waterman
57e82442a1 Make LoadGen and StoreGen generic 2015-11-24 18:12:42 -08:00
Howard Mao
ee6514e4f4 make sure WritebackUnit sends correct probe addresses 2015-11-21 15:55:11 -08:00
Howard Mao
04383a31f5 Revert "make sure L2MetadataArray assigns unoccupied way if available" 
This reverts commit 1857f36c1e6f2b2859c724eea6ae3cfb2618f81b.
 2015-11-21 10:35:40 -08:00
Howard Mao
3c95afebc6 Shift set index for multi-bank configurations 
Prior to this commit, the L2 cache banks used the lower bits of the
block address as the set index. However, the lower bits are also used to
route addresses to different banks. As a result, in multi-bank
configurations, only a fraction of the sets in each bank could be
accessed. This commit fixes that problem by using the bits ahead of the
bank index as the set index, so that all sets in the cache can be
accessed.
 2015-11-20 23:24:57 -08:00
Howard Mao
55a85cc67a make sure wmask is passed for PutBlock in broadcast hub 2015-11-20 14:09:24 -08:00
Howard Mao
941b64cd62 make partial write-masking PutBlock constructor always set alloc bit 2015-11-20 13:34:07 -08:00
Howard Mao
24f7b9f472 make sure L2MetadataArray assigns unoccupied way if available 2015-11-19 10:45:54 -08:00
Howard Mao
e50c7ad306 add NASTI error assertions back in 2015-11-18 17:05:54 -08:00
Henry Cook
2b977325e3 Make prefetch type available in a_type, issue probeInvalidates for putPrefetches 2015-11-16 23:26:13 -08:00
Andrew Waterman
d426ecee78 Remove IPI network 
This is now provided via MMIO.
 2015-11-16 21:52:24 -08:00
Henry Cook
0290635454 amo_shift_bits -> amo_shift_bytes 2015-11-16 19:07:58 -08:00
Henry Cook
64aaf71b06 L2AcquireTracker refactor to support merging Gets and Puts into Prefetches of the correct type. 
Transaction metadata for primary and seconday misses now stored in the secondary miss queue.

Added BuiltInAcquireBuilder factory.
 2015-11-16 18:10:09 -08:00
Henry Cook
03fa06e6e7 fix prefetch lockup on L2 hit 2015-11-15 12:51:34 -08:00
Howard Mao
e12efab423 skip meta_write state if no meta write pending 2015-11-13 13:50:35 -08:00
Howard Mao
7e7d688a01 make sure L2 passes no-alloc acquires through to outer memory 2015-11-12 15:40:58 -08:00
Howard Mao
b3865c370a make sure correct addr_beat is sent for Get response by narrower/converter 2015-11-12 15:40:38 -08:00
Howard Mao
f397d61033 add alloc option to Put constructor 2015-11-12 11:39:59 -08:00
Howard Mao
7733fbe6a3 make sure no-alloc write still updates data array if there is a cache hit 2015-11-12 11:39:36 -08:00
Howard Mao
b59ce5fed4 make sure L2 waits for outer grant before sending grant for write request 2015-11-10 16:06:14 -08:00
Howard Mao
42d3d09d7a add a ClientTileLinkEnqueuer to complement the TileLinkEnqueuer 2015-11-09 11:49:19 -08:00
Howard Mao
7942be4e01 make sure outerTL method is idempotent 2015-11-09 11:10:02 -08:00
Henry Cook
e3efc09b5b remove unnecessary UInt encode/decode on releaseMatches path 2015-11-05 17:20:03 -08:00
Henry Cook
3698153535 OHToUInt instead of PriorityEncoder on Acq/RelMatches signals in L2Bank 2015-11-03 14:31:35 -08:00
Howard Mao
baa2544651 Fix some more issues with narrower 2015-10-31 19:36:30 -07:00
Howard Mao
812c5bcc55 make sure narrower can handle sub-block level requests correctly 2015-10-31 15:58:36 -07:00
Howard Mao
d4b8653002 fix too strict assertion in broadcast hub 2015-10-31 15:58:10 -07:00
Howard Mao
c10870a87c make sure ID width requirement in TL -> NASTI converter is correct 2015-10-27 13:25:29 -07:00
Howard Mao
9fa4541916 get rid of unused full signal in ReorderQueue 2015-10-26 12:17:25 -07:00
Howard Mao
6403f27fbe fix bug in ReorderQueue breaking TileLink Unwrapper 2015-10-22 15:52:55 -07:00
Jim Lawson
4c2b0a9032 Add ability to generate libraryDependency on cde. 2015-10-22 09:57:02 -07:00
Henry Cook
f8594da1d3 depend on external cde library 2015-10-21 18:17:17 -07:00
Howard Mao
02d113b39f outerDataBits / innerDataBits should be per beat, not per block 2015-10-21 11:31:13 -07:00
Howard Mao
baf95533a4 fix combinational loop in TileLink Unwrapper 2015-10-20 23:26:11 -07:00
Howard Mao
ffe7df2fed make sure TL -> NASTI converter acquire ready not dependent on valid 2015-10-20 22:09:22 -07:00
Howard Mao
1c135c1628 fix ready-valid mixup in TileLink unwrapper 2015-10-20 21:07:42 -07:00
Henry Cook
4389b9edb0 tilelink parameter tweak: addrBits now a constant 2015-10-20 15:00:30 -07:00
Howard Mao
d12403e7dc fix up and simplify TL -> NASTI converter logic 2015-10-19 13:47:13 -07:00
Henry Cook
d391f97953 Minor refactor of StoreGen/AMOALU. Bugfix for 32b ops in L2's AMOALU. 2015-10-16 19:11:06 -07:00
Henry Cook
e1f573918d simplify TileLinkParameters with Option 2015-10-16 18:24:38 -07:00
Howard Mao
49667aa4b0 make sure broadcast acquire tracker doesn't try to send requests back-to-back 2015-10-14 18:56:13 -07:00
Howard Mao
1d362d6d3a make sure correct parameters are used for TileLink constructors 2015-10-14 17:58:54 -07:00
Henry Cook
7fa3eb95e3 refactor tilelink params 2015-10-14 12:13:37 -07:00
Henry Cook
66ea39638e GlobalAddrMap 2015-10-14 00:23:28 -07:00
Henry Cook
31be6407ec Removed all traces of params 2015-10-14 00:23:28 -07:00
Henry Cook
908922c1a4 refactor NASTI to not use param 2015-10-14 00:23:28 -07:00
Howard Mao
47da284e56 TileLinkNarrower should do nothing if interfaces are the same width 2015-10-13 13:28:47 -07:00
Howard Mao
83df05cb6a add TileLink data narrower 2015-10-13 12:45:39 -07:00
Howard Mao
993ed86198 move ReorderQueue to utils.scala 2015-10-13 09:49:22 -07:00
Andrew Waterman
0fe16ac1c0 Chisel3 compatibility fixes 2015-09-30 14:37:00 -07:00
Howard Mao
1e7f656527 get release block address from inner release 2015-09-28 15:02:51 -07:00
Andrew Waterman
3b1da4c57e Revert "replace remaining uses of Vec.fill" 
This reverts commit b6bb4e42127d1ed42b55ec8b859a4e074b347d47.
 2015-09-25 17:06:57 -07:00
Andrew Waterman
20b7a82ab6 Use Vec.fill, not Vec.apply, when making Vec literals 2015-09-25 17:06:52 -07:00
Andrew Waterman
2179cb64ae Let isRead be true for store-conditional 
This works around a deadlock bug in the L1 D$, and is arguably true.
 2015-09-25 15:28:02 -07:00
Howard Mao
308022210a use updated NASTI channel constructors 2015-09-25 12:07:27 -07:00
Howard Mao
8c4ac0f4f3 make sure CSR/SCR data width matches xLen 2015-09-25 12:07:03 -07:00
Howard Mao
d1f2d40a90 replace remaining uses of Vec.fill 2015-09-24 17:50:09 -07:00
Howard Mao
3ff830e118 ReorderQueue uses Vec of Bools instead of Bits for roq_free 2015-09-24 17:43:53 -07:00
Howard Mao
83740dfaa5 Merge branch 'master' of github.com:ucb-bar/uncore 2015-09-24 17:10:09 -07:00
Howard Mao
3b86790c3f replace NASTIMasterIO and NASTISlaveIO with NASTIIO 2015-09-24 16:58:20 -07:00