ebffd69b8e
This was recently changed to write out physical addresses for SCR file entries, but to bring up the chip we need SCR offsets so we can write the uncore SCR file over HTIF. This changes the map generator to generate both. Without this change things happened to work anyway because the high bits were getting dropped by the SCR file. |
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| project | ||
| src/main/scala | ||
| .gitignore | ||
| build.sbt | ||
| LICENSE | ||
| README.md | ||
Uncore Library
This is the repository for uncore components assosciated with Rocket chip project. To uses these modules, include this repo as a git submodule within the your chip repository and add it as a project in your chip's build.scala. These components are only dependent on the ucb-bar/chisel repo, i.e.
lazy val uncore = project.dependsOn(chisel)
ScalaDoc for the uncore library is available here and an overview of the TileLink Protocol is available here, with associated CoherencePolicy documentation here.