3c95afebc6
Prior to this commit, the L2 cache banks used the lower bits of the block address as the set index. However, the lower bits are also used to route addresses to different banks. As a result, in multi-bank configurations, only a fraction of the sets in each bank could be accessed. This commit fixes that problem by using the bits ahead of the bank index as the set index, so that all sets in the cache can be accessed. |
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| src/main/scala | ||
| .gitignore | ||
| build.sbt | ||
| LICENSE | ||
| README.md | ||
Uncore Library
This is the repository for uncore components assosciated with Rocket chip project. To uses these modules, include this repo as a git submodule within the your chip repository and add it as a project in your chip's build.scala. These components are only dependent on the ucb-bar/chisel repo, i.e.
lazy val uncore = project.dependsOn(chisel)
ScalaDoc for the uncore library is available here and an overview of the TileLink Protocol is available here, with associated CoherencePolicy documentation here.